CHIPMAKER INTEL has spilled more details about the Goldmont microarchitecture that will power the firm's 14nm Atom, Pentium and Celeron microprocessors.
The new information comes after Intel updated its x86-64 programming guides, providing developers with more information about Goldmont.
The microarchitecture was launched at the Intel Developer Forum in China in April, and the company has made clear that it will be used predominantly at the lower end as part of the Apollo Lake platform.
Goldmont will provide about 30 per cent better CPU performance and improved battery life compared with Silvermont. Architecturally it has three decoder units (to its predecessor's two) and a maximum of 20 bytes decoded per cycle, according to ExtremeTech.
"The fetch and instruction cache pipelines are no longer coupled, large page support has been added, and there's a small L2 'precode' cache (16K) that didn't exist on prior Atom processors," said ExtremeTech.
"Goldmont's triple-wide decoder is matched by its ability to retire up to three instructions per cycle, and the chip is capable of executing one load and store per clock cycle. Three simple integer operations can be executed per cycle, and address generation is now out-of-order in Goldmont."
Goldmont will therefore generally offer improved instruction latencies but provide smaller performance gains over its predecessor, which isn't surprising given the length of time since Silvermont was introduced in 2013.
The shift from 22nm to 14nm process manufacturing for Goldmont parts is also a smaller shift than from Bonnell (at 45nm cores) to Silvermont (at 22nm).
Intel also hopes to propagate Goldmont-based CPUs in the emerging Internet of Things category.
Intel unveiled one of the first devices based on Goldmont, the Atom E3900, last month, which the company billed as "edge-to-cloud network computing".
Unlike typical low-power consumption parts intended for connected devices, the Intel Atom has 3D graphics, improved by 2.9 times compared with the previous Atom generation, and can support three independent displays, according to Intel. µ
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