INTEL HAS QUIETLY revealed plans to dump its relentless 'tick-tock' approach to microprocessor development as the company nears the limits of what can be achieved with copper on silicon.
The firm has instead outlined plans for a three-pronged development process described as 'process architecture optimisation'.
The plans were tucked away in Intel's latest annual report, and represent an admission that the company is struggling to produce the same performance upgrades year after year that have made it such a dominant force in semiconductors.
Intel's tick-tock approach referred to a year-by-year cycle in which it upgraded manufacturing techniques one year and upgraded microprocessor architectures the next.
The approach meant that Intel could wring out performance improvements year after year through better manufacturing one year and architectural improvements the next.
Rival AMD has been left trailing in Intel's wake, unable to keep up with the sheer resources that the chip maker can pour into manufacturing, which becomes increasingly complicated the closer Intel (and other manufacturers) get to the 6nm limit imposed by the laws of physics.
AMD sold off its capital-intensive manufacturing plants in 2010 to focus on design, but this provided only temporary financial respite for the company.
Intel shifted to 14nm transistors with the belated launch last year of the Broadwell line of microprocessors (the tick) and introduced the Skylake line-up this year (the tock). Both microprocessor lines were delayed.
Following on from Skylake, Intel had planned to introduce Kaby Lake chips produced on 10nm process architectures but will instead stick with current 14nm manufacturing techniques. The firm has promised that the Cannonlake line of microprocessors, scheduled for the second half of 2017, will debut on 10nm.
Intel admitted in its annual report: "We expect to lengthen the amount of time we will use our 14nm and our next-generation 10nm process technologies, further optimising our products and process technologies while meeting the yearly market cadence for product introductions."
At the same time, CEO Brian Krzanich suggested recently that that the cadence for "technology transitions" is lengthening from two to 2.5 years, and that the physical limits will probably be reached at around the 6nm mark in the next five years. In context, a strand of DNA measures about 2.5nm in diameter.
Intel has instead introduced a third element in the process that it calls 'optimisation' to extract extra performance improvements from manufacturing and architecture. It's effectively an admission that it cannot drive performance improvements at the rate that it has done over the past three decades or so. µ
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