Based on 48 layers of three-bit multi-level cell (MLC) arrays for use in solid state drives (SSDs), Samsung's 256Gb 3D V-NAND flash doubles the density of conventional 128Gb NAND flash chips.
The new V-NAND chip consists of cells that use the same 3D Charge Trap Flash structure in which the cell arrays are stacked vertically to form a 48-story mass that is connected electrically through some 1.8 billion channel holes, punching through the arrays thanks to a special etching technology.
Samsung said that each chip contains over 85.3 billion cells, which can store three bits of data each, resulting in 256 billion bits of data in total, "in other words, 256Gb on a chip no larger than the tip of a finger".
A 48-layer three-bit MLC 256Gb V-NAND flash chip delivers more than a 30 percent reduction in power compared with a 32-layer, three-bit MLC, 128Gb V-NAND chip when storing the same amount of data.
The new chip also achieves approximately 40 percent more productivity over its 32-layer predecessor during production, bringing greatly enhanced cost competitiveness to the SSD market while mainly using existing equipment.
In addition to enabling 256Gb, or 32GB, of memory storage on a single die, the firm's new chip is said to double the capacity of Samsung's existing SSD line-ups, providing a better resolution for multi-terabyte SSDs.
"With the introduction of our third-generation V-NAND flash memory to the global market, we can now provide the best advanced memory solutions, with even higher efficiency based on improved performance, power use and manufacturing productivity, thereby accelerating growth of the high-performance and the high-density SSD markets," said Young-Hyun Jun, president of Samsung's memory business.
"By making full use of Samsung V-NAND's excellent features, we will expand our premium-level business in the enterprise and data centre market segments, as well as in the consumer market, while continuing to strengthen our strategic SSD focus."
Samsung introduced the second-generation V-NAND chips a year ago, which consisted of a 32-layer three-bit MLC, and has patted itself on the back for ushering in the next generation "in just one year".
The Korean chip maker plans to produce third-generation V-NAND throughout the remainder of 2015 in a bid to accelerate the adoption of terabyte-level SSDs. Samsung also plans to increase its high-density SSD sales for the enterprise and data centre storage markets with PCIe NVMe and SAS interfaces.
The announcement comes just days after Toshiba and SanDisk started production of the first 48-layer Bit Cost Scalable (BiCS) flash memory chip.
The joint venture, announced in March, will begin pilot production of BiCS, a two bit per cell, 128Gb (16GB) device with a 3D-stacked cell structure flash, in the second half of this year as planned.
BiCS is said to improve density and significantly reduce the overall size of the chip, and uses a 'charge trap' that stops electrons leaking between layers, improving the reliability of the product.
Toshiba is already using 15nm dies so, despite the layering, the finished product will be competitively thin and is expected to find its way into the usual suspects, including consumer and enterprise SSD drives, smartphones, tablets and memory cards.
Intel and Micron also announced big plans in memory for the year ahead. The firms have promised to deliver 3D NAND flash memory that has three times the capacity of that currently on the market, which is sampling now and is said to allow for up to 10TB SSDs in a standard 2.5in format. µ
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