CARBON NANOTUBES have many benefits over traditional silicon. Transistors in silicon have been made smaller year after year but are approaching a physical limit, and shrinking the size of the transistor, including the channels and contacts, without compromising performance is becoming increasingly difficult.
However, carbon nanotube chips could improve the capabilities of high-performance computers because they allow these contacts to be so small that they are virtually transparent. This means that the size of the semiconductor can be decreased dramatically, while the substrate of carbon nanotubes makes the chip more energy efficient and is a soft and flexible material that could allow new device form factors.
The arrangement of these contacts, and thus the ability for these types of chip to decrease in size, allows them to be built in different forms.
One way in which Stanford University is exploring this is by using carbon nanotube technology in high-rise chip architecture processes. Working alongside other universities, Stanford engineers have created this new technology, which it calls Nano-Engineered Computing Systems Technology, or N3XT.
"For decades, engineers have designed computer systems with processors and memory chips laid out like single-story structures in a suburb," explained the university when announcing the breakthrough. "Wires connect these chips like streets, carrying digital traffic between the processors that compute data and the memory chips that store it. But suburban-style layouts create long commutes and regular traffic jams in electronic circuits, wasting time and energy."
N3XT looks to break these data bottlenecks by integrating processors and memory like floors in a skyscraper and connecting components with millions of 'vias' that play the role of tiny electronic lifts. If all goes to plan, the N3XT high-rise approach could move more data, much faster, using far less energy, than would be possible using low-rise circuits.
"We have assembled a group of top thinkers and advanced technologies to create a platform that can meet the computing demands of the future," said Subhasish Mitra, associate professor at Stanford's Department of Electrical Engineering and Department of Computer Science, who has been working on the project for some time. His thinking is that shifting electronics from a low-rise to a high-rise architecture will demand huge investments from the industry and offer the promise of big payoffs.
"When you combine higher speed with lower energy use, N3XT systems outperform conventional approaches by a factor of 1,000," added Professor Philip Wong, who leads the project.
Wong explained that these increases in performance are down to the use of new nano-materials that allow designs that can't be achieved with silicon.
A problem with fabricating silicon chips is that the process requires temperatures close to 1,800 degrees Fahrenheit, making it extremely challenging to place a silicon chip on top of another without damaging the first layer. To overcome this, the current approach is to develop 3D chips, or ‘stacked' chips, as we've seen from Samsung in the past few years. These are constructed with two separate silicon chips which are then stacked and connected with a few thousand wires. But 3D silicon chips are still prone to traffic jams, and it takes a lot of energy to push data through what are a relatively few connecting wires.
This is why Stanford's N3XT team is taking a different approach when building layers of processors and memory directly on top of each other. These chips are different because they are connected by millions of electronic lifts that can move more data over shorter distances than traditional wire, using less energy. N3XT therefore immerses computation and memory storage into an electronic 'super-device'.
"The key is the use of non-silicon materials that can be fabricated at much lower temperatures than silicon, so that processors can be built on top of memory without the new layer damaging the layer below," explained the university.
N3XT high-rise chip architectures are able to work because they are made of carbon nanotube transistors (CNTs). These transistors are the tiny on-off switches that create digital zeroes and ones. CNTs are faster and more energy-efficient than silicon processors and can be fabricated and placed over and below other layers of memory.
It's not only the structure of the new chips that resembles a skyscraper, as the process gives them ventilation systems like those used in tall buildings. N3XT high-rise chip designs incorporate thermal cooling layers which ensure that the heat rising from the stacked layers of electronics does not degrade overall system performance.
But it's not just faster processors that N3XT's work could create. Some of the engineers working on the project believe that using data storage technologies that rely on materials other than silicon are also a possibility because they could be manufactured on top of CNTs using low-temperature fabrication processes.
One such data storage technology is resistive random access memory, or RRAM. The N3XT team is also experimenting with a variety of nano-scale magnetic materials to store digital ones and zeroes.
Future for N3XT
The N3XT team's latest research paper demonstrates that it can run simulations showing how the high-rise approach is 1,000 times more efficient in carrying out many important and highly demanding industrial software application tasks. But the next stage is to get the chips in a stable position so that they can change the computing world.
Stanford computer scientist and N3XT co-author Chris Ré explained that the new chip design could help solve many of the globe's data problems.
"There are huge volumes of data that sit within our reach and are relevant to some of society's most pressing problems from healthcare to climate change, but we lack the computational horsepower to bring this data to light and use it," he said. "As we all hope in the N3XT project, we may have to boost horsepower to solve some of these pressing challenges."
Not the first time
The idea of using carbon nanotubes in chips is by no means a new idea. IBM's research and development department announced "a major engineering breakthrough" in transistor technology in October after scientists demonstrated a new way to shrink transistor contacts in chips.
By speeding up the replacing of silicon transistors with carbon nanotubes, which the firm has been working on for several years, IBM said that the breakthrough brings the firm closer to creating a fully scaled carbon nanotube technology that will power future computers while increasing performance and "opening a pathway to dramatically faster, smaller and more powerful chips".
Shu-jen Han, IBM's manager of nanoscale science and technology, told The INQUIRER in an interview that wearable technology is one of the most exciting areas that this technology could transform owing to the unique property of the substrate, allowing new form factors with better performance and battery life.
However, the breakthrough isn't about the carbon nanotube material being a better replacement for silicon, but more of an engineering innovation that addresses part of the problem in successfully rolling out better-performing and more efficient chips.
"We know what the issue has been, and the limits of the technology, for years. What we solved here is a device-level issue, a one-dimensional structure. We need to make a wafer of them, a high-quality wafer, which does not exist yet," said Shu-jen.
The next stage for IBM's research group is to scale up the carbon nanotube technology to make reliable mass produced chips so that they can make a difference to businesses and consumers.
Shu-jen explained that this could take five to 10 years, but could enable big data to be analysed faster and allow cloud data centres to deliver services more efficiently and economically. µ
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