CHIPMAKER Intel has launched its 22nm Xeon E5-2400 v2 family of processors for servers and workstations, a lower specification version of the Xeon E5-2600 the firm launched at its Intel Developer Forum (IDF) last September.
Updating the chip to the 22nm Ivy Bridge core architecture, the Xeon E5-2400 v2 is the successor to the existing E5-2600 line based on Sandy Bridge technology and brings improvements in performance plus a focus on power efficiency.
Previously codenamed Ivy Bridge-EN, the E5-2400 family includes 12 models that serve as drop-in replacements for existing servers using the Xeon Sandy Bridge v2 series chips, featuring up to 10 cores that support two-socket server, storage and communication systems.
"The E5-2400 v2 product family brings down the TDP to 50W, [a] lower TDP SKU is especially useful for embedded designs in the communications market where the system power envelope is constrained," Intel director of server platform marketing Dylan Larson said in a blog post.
"These lower TDP processors can also be integrated into very dense server racks and blades, and can help to drive up compute density and help drive down TCO."
The Xeon E5-2400 v2 product family includes storage extensions such as Asynchronous DRAM Refresh and x16 Non-transparent bridging, which Intel claims help to enhance data protection and replication for storage uses.
"The product family provides the performance, I/O, and memory capabilities for a wide range of compute-intensive embedded and communications applications, including: servers, blades, and appliances for communications infrastructure; medical, storage systems, and security applications; carrier-grade rack-mount servers; and proprietary form factors, such as router modules," Larson added.
Intel's higher specification flagship Xeon E5-2600 v2 server chip was announced at IDF in San Francisco last year touting better performance, updated memory bandwidth and improved security features. It also comes in three separate die flavours: One for four to six-core chips with 15MB of shared L3 cache, another for six to 10 cores with 25MB of L3 cache, and the third for the 12-core chips with 30MB of L3 cache, targeting maximum performance. µ
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