KOREAN CHIP MAKER Samsung has begun mass producing DDR4 memory for enterprise servers in data centres.
Claiming that the memory is "the most advanced" of its kind, the high-performance, high-density DDR4 modules use 20 nanometer (nm) class process technology as opposed to the conventional DRAM of 8Gb modules that use a 30nm class process technology.
The 4Gb DDR4 has a DRAM data transmission rate of 2,667 megabits per second, which Samsung said is a 1.25-fold increase over 20nm class DDR3, while also lowering power consumption by over 30 percent.
Samsung last updated its line-up of memory with 50nm-class 2Gb DDR3 back in 2008. Samsung claims that its fresh DDR4 RAM will boost performance of enterprise servers at the system level while lowering overall power consumption.
The Korean company thinks that early market availability of 4Gb DDR4 devices will also help push 16GB and 32GB memory modules, while allowing the firm to "support the need for advanced DDR4 in rapidly expanding, large-scale data centres and other enterprise server applications".
"The adoption of ultra-high-speed DDR4 in next-generation server systems this year will initiate a push toward advanced premium memory across the enterprise," Samsung's EVP of memory sales Young-Hyun Jun said.
"After providing cutting-edge performance with our timely supply of 16GB DDR3 earlier this year, we are continuing to extend the premium server market in 2013 and will now focus on higher density and added performance with 32GB DDR4, and contribute to even greater growth of the green IT market in 2014."
Earlier this month, Samsung revealed it had started mass-producing 3D vertical NAND or "V-NAND" chips after 10 years of research and development.
The technology, which is also being worked on by many other chip makers such as Micron and Intel, enables memory cells to be stacked on top of each other vertically on the same chip, instead of spread out in a two-dimensional (2D) horizontal grid.
Samsung claimed that its new V-NAND offers a 128Gb density in a single chip by using a proprietary vertical cell structure based on 3D Charge Trap Flash (CTF) technology and vertical interconnect process technology "to link the 3D cell array". µ