KOREAN CHIP MAKER Samsung announced the mass production of 3D vertical NAND or "V-NAND" chips today after 10 years of research and development.
The technology, which is also being worked on by many other chip makers such as Micron and Intel, enables memory cells to be stacked on top of each other vertically on the same chip, instead of spread out in a two dimensional (2D) horizontal grid.
Until this point 3D NAND was just a concept. Memory makers crowed about research but remained very tight-lipped about future plans.
"Achieving gains in performance and area ratio, the new 3D V-NAND will be used for a wide range of consumer electronics and enterprise applications, including embedded NAND storage and solid state drives (SSDs)," the Korean manufacturer said in a statement today.
Samsung claimed that its new V-NAND offers a 128Gb density in a single chip by using a proprietary vertical cell structure based on "3D Charge Trap Flash" (CTF) technology and vertical interconnect process technology "to link the 3D cell array".
Samsung said that these two separate technologies allow its 3D V-NAND chips to provide over twice the scaling of 20nm class planar NAND flash.
"Following the world's first mass production of 3D Vertical NAND, we will continue to introduce 3D V-NAND products with improved performance and higher density, which will contribute to further growth of the global memory industry," Samsung added.
Over the last 40 years or so NAND flash cells have been fabbed in two dimensions. Scaling down the chips has proven difficult as memory makers have shrunk the X and Y dimensions to develop from one chip generation to the next.
There have also been concerns from chipmakers that such scaling has caused the difference between states within a memory cell to decline to the order of 10 or 20 electrons. Electrons don't work well in smaller numbers, so not only have manufacturers approached fundamental limits but this had led to added development time and costs.
However, Samsung's breakthrough aims to solve these technical challenges with new circuit structures.
It said, "To do this, Samsung revamped its CTF architecture, which was first developed in 2006. In Samsung's CTF-based NAND flash architecture, an electric charge is temporarily placed in a holding chamber of the non-conductive layer of flash that is composed of silicon nitride (SiN), instead of using a floating gate to prevent interference between neighbouring cells."
Samsung said that making this CTF layer three-dimensional improved the reliability and speed of the NAND flash memory.
"The new 3D V-NAND shows not only an increase of a minimum of 2X to a maximum 10X higher reliability, but also twice the write performance over conventional 10nm-class floating gate NAND flash memory," it added.
Samsung boasted that the V-NAND can also stack as many as 24 cell layers vertically due to its "proprietary vertical interconnect process technology", which uses etching technology to connect the layers electronically by punching holes from the top layer to the bottom layer.
"We can enable higher density NAND flash memory products by increasing the 3D cell layers without having to continue planar scaling, which has become incredibly difficult to achieve," the company claimed.
When we quized Samsung as to what sorts of products it plans on using the new 3D V-NAND chips in first, it told us that it will be used for "a wide range of consumer electronics and enterprise applications, including embedded NAND storage and solid state drives (SSDs)".
It was just last week that we spoke with American memory maker Micron, which also said it has been working on 3D NAND technology. Micron's VP of NAND Solutions Glen Hawk claimed that 3D NAND is the "next revolution" in data storage and is opening up "a new era of scaling" for the firm. µ
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