The difference between [the P4] and the [Athlon] die size is frigging huge - AMD's Jerry Sanders III
CHIPMAKER Toshiba has developed a multi-level MROM cell citing improved performance characteristics.
Toshiba's MROM cell is designed to store the bootloader or firmware of a device and development as been focused on how to reduce power usage without increasing physical size because it is put into system on chip (SoC) designs. The firm said its new multi-level MROM cell provides twice the memory capacity of a single-level cell without increasing the cell footprint.
Toshiba said its multi-level MROM cell has three times the channel width in the cell transistors over a single-level MROM cell. The firm claimed it tripled the current characteristic of the cell without any changes to memory density and reduced variation in fabrication by 42 percent.
Toshiba like other chip designers is battling to improve the performance characteristics of SoC parts as more functionality is being pushed onto single pieces of silicon. As SoCs become ever more complex, chip firms need to ensure that chips remain economically viable to manufacture while increasing performance, which is why Toshiba was keen to stress the reduction in fabrication variance.
According to Toshiba, it has developed its multi-level MROM cell using a 40nm process node and the firm aims to ship SoCs including the MROM cell in 2014. The firm is presenting the technology at the VLSI Technology and Circuits conference this week. µ
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