SILICON DESIGN AND VERIFICATION OUTFIT Mentor Graphics has announced that its Calibre software product has passed initial design reference and SPICE modeling tool certification for TSMC's upcoming 16nm FinFET process node.
TSMC has been doing a roaring trade on its 28nm process node, however the firm has been working on its next generation 16nm FinFET process node, which is expected to start stamping out its first production wafers in the next year or so. Mentor Graphics has announced that its Calibre chip design and verification technology is on the first step to fully supporting TSMC's 16nm FinFET process node.
While TSMC is busy researching and deploying its next generation process node, chip designers need to be able to verify that their designs will work when produced on TSMC's process node. Mentor Graphics' Calibre software supports design rule definition and lithography hotspot pre-filtering as well as TSMC's very specific filling requirements for its FinFET process node.
TSMC's 16nm FinFET process node fabs 3D transistors like Intel uses on its 22nm process node. Intel's Ivy Bridge processors that it launched last year were the first to make use of FinFET transistors, and Intel is going to use a modified version of its 22nm process node for its upcoming Haswell processors.
Joseph Sawicki, VP and GM of the Design to Silicon division at Mentor Graphics said, "We've worked closely with TSMC to understand the impact of FinFETs and their interaction with other innovations, such as multi-patterning, on the physical design flow. Enhancing our products to handle 16nm FinFET requirements transparently helps designers stay focused on using the new process capabilities to create more value for their customers."
What Mentor's Calibre software does is allow chip design firms looking to work with TSMC and its upcoming 16nm process node get started on verifying their designs ahead of process availability. µ
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