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Hypercube stacked DRAM specification is finalised

Aims to bring down the DRAM wall
Wed Apr 03 2013, 14:38
An Intel Xeon processor -- 2012's Sandy Bridge

THE HYBRID MEMORY CUBE (HMC) consortium has announced that its members have agreed on a final specification for stacked memory.

The HMC consortium is made up of just about every major DRAM maker including Samsung, SK Hynix and Micron Technology, and has been looking at ways of stacking memory modules to increase capacity and performance. Now the consortium has said its members have agreed on a final specification that its members can look at implementing.

Chip vendors such as Nvidia have been talking up the advantages of stacking DRAM chips in terms of performance and it has been working with DRAM vendor SK Hynix to make this possible. However SK Hynix has been working with various other HMC members to come to a short-term solution to the so-called DRAM wall, which limits capacity and performance due to physical constraints.

Jim Elliott, VP of memory planning and product marketing at Samsung Semiconductor said, "The consensus we have among major memory companies and many others in the industry will contribute significantly to the launch of this promising technology.

"As a result of the work of the HMC consortium, IT system designers and manufacturers will be able to get new green memory solutions that outperform other memory options offered today."

Elliott wasn't the only one trumpeting the final specification, with his counterparts from Micron and SK Hynix doing the same. Given the make-up of the HMC consortium, which also includes firms such as ARM, IBM and HP, it seems almost inevitable that the specification will end up being implemented.

The HMC consortium said its next goal is to increase bandwidth for short reads and ultra short reads to 28Gb/sec and 15Gb/sec, respectively. The consortium claimed that the next revision of its HMC specification should be agreed by the first quarter of 2014. µ


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