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Toshiba claims SRAM chip cuts power consumption by 85 percent

Cites MP3 decode on smartphones as a possible use
Fri Feb 22 2013, 17:33
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CHIPMAKER Toshiba announced a low-power embedded SRAM memory chip that it claims reduces power consumption by up to 85 percent.

Toshiba's memory chip operations have seen it supply DRAM and NAND flash chips to a number of smartphone and tablet makers, but the giant Japanese firm is also developing its older and perhaps less fashionable SRAM technology. The firm announced at the IEEE International Solid State Circuit Conference that it has developed an SRAM chip that it claims reduces both active and standby power consumption by 27 percent and 85 percent, respectively.

Toshiba said its new SRAM chip uses a bit line power calculator (BLPC) and a digitally controllable retention circuit (DCRC) to achieve the power savings. The firm's technology uses the BLPC to predict the power consumption of bit lines and monitors the current consumption of the SRAM rest circuits, while the DCRC decreases standby power by updating the size of the buffer in the retention driver.

Toshiba said, "As low performance applications require only tens of MHz operation, SRAM temperature remains around room temperature, where active and leakage power consumptions are comparable. Given this, the key issue is to reduce active and standby power from high temperature to room temperature."

According to Toshiba, its SRAM chips can be used in smartphones, but it said that use cases such as MP3 decode and background processing could make use of its new low-power SRAM chips. µ

 

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