SAN FRANCISCO: THIS YEAR there wasn't a single processor paper by Intel at ISSCC, but there was a very interesting paper on rapid I/O technology that combines scalability with significant power savings.
Minimizing I/O cost, area and power are crucial to achieving a practically realisable system with high bandwidth. To meet these needs, Intel has developed a low power, dense 64-lane I/O system with per port aggregate bandwidth up to 1Tbit/s and 2.6pJ/bit power efficiency.
In addition to the interconnect Intel has also developed a high density connector and cable attached to the top side of the package.
We have previously seen fast interconnects, but the news this time around is the density as well as the scalability. It is possible to vary the lane data rate from 2Gbit/s to 16Gbit/s on the fly.
This provides scalable aggregate bandwidth of 128Gbit/s to 1Tbit/s with a power efficiency of 0.8pJ/bit to 2.6pJ/bit, or to put it very simply, you can adjust the bandwidth to whatever your needs are - and when you don't need a lot of bandwidth you save power instead of running at full tilt.
The cable that Intel uses has a maximum length of 50cm and can be used either to connect processors or to connect a processor to a DRAM subsystem in order to feed the processor with data. µ
Plus the cost of ambition as moonshots eat into the coffers
Spoiler alert: it's probably VeriSign
Did we say cuts off? We meant traps them inside their own home