SAN FRANCISCO: YOU MIGHT AS WELL get used to the codename Jaguar from AMD, if the firm's presentation at the International Solid State Circuits Conference (ISSCC) in San Francisco is anything to go by.
Jaguar is the successor to Bobcat, will be fabbed at 28nm and is meant for mobile devices, as chips employing the Jaguar architecture will consume from below 5W to 25W of power.
The smallest unit in the Jaguar architecture is a Compute Unit, also known as a CU. Each CU consists of four cores, each with a 512KB cache. Bobcat also had a 512KB cache, but it could only be accessed by the local core. In Jaguar the cache is shared between all four cores.
During its presentation AMD did not directly talk about processors with more than four cores, but it hinted at possible future chips with more than one CU, opening the way for six-core and even eight-core chips.
Jaguar has improvements over Bobcat in terms of instructions per cycle (IPC), clock frequency, and power consumption. The load-store unit has been redesigned for significant performance and power improvements over AMD’s previous generation products, and the floating point unit natively supports 128-bit operation, according to the presentation.
The Jaguar core silicon has, according to AMD, demonstrated full functionality at frequencies above 1.85GHz, but might be constrained by system on chip (SoC) power budgets, which in some cases are below 0.5W per core. µ