SAN FRANCISCO: WE HAVE HEARD many rumours about the T5 SPARC processor, but now more details are available, thanks to an announcement at the International Solid State Circuits Conference (ISSCC) on Monday.
The T5 is clocked at 3.6GHz, has 16 cores and is fabbed on a 28nm process by TSMC. It contains 1.5 billion transistors and 13 metal layers. Each core is capable of running eight threads simultaneously, making it capable of executing 128 threads in total.
There are major advances over the T4, but apparently the T5 has also caused Oracle a few headaches, as the chip is late.
The cores communicate via a high-bandwidth nine-port crossbar switch and share an 8MB, eight-bank L3 cache. The DDR3 memory subsystem supports nearly three times the bandwidth of the previous generation through the combination of a new memory controller, 12.8Gbit/s per lane memory links and a companion buffer chip, according to Oracle.
In addition the die also contains a Gen3 PCI Express controller that supports 32GB/s peak bandwidth full duplex operation per socket through dual ports.
The T5 is of course meant to go into the datacentre and is optimized for executing Oracle's database and applications software.
It is seen as a competitor to Intel's Itanium, which uses a CISC architecture as opposed to the T5, which is based on a RISC architecture. µ
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