CHIP SHOP TSMC announced it has taped out its first chip on wafer on substrate (COWOS) test vehicle using the wide I/O mobile DRAM interface.
TSMC has been promoting its COWOS process after it announced a 20nm process using the technology earlier this week. Now the firm said it has taped out a COWOS test vehicle using JEDEC's wide I/O mobile DRAM standard.
TSMC's COWOS process allows system-on-chip (SoC) parts to have DRAM placed on the same module using JEDEC's wide I/O interface. TSMC claims this integration provides higher performance, decreases the physical size requirements and improves die-to-die bandwidth.
Cliff Hou, VP of research and development at TSMC said, "Silicon validation is a critical step in the development of a highly advanced and complete COWOS design solution. The successful demonstration of the JEDEC Wide I/O mobile DRAM interface highlights the significant progress TSMC and its ecosystem partners have made to capitalize on the performance, energy efficiency and form factor advantages of CoWoS technology."
TSMC also highlighted the roles played by DRAM maker SK Hynix, design tool outfit Mentor Graphics and wide I/O DRAM design firm Cadence Design Systems. The company said that COWOS has now entered the pilot production stage but didn't say when it will begin stamping out customer designs. µ
Or so says the rumour mill ...
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