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TSMC announces two 20nm reference flows for chip designers

Preparing the ground for 20nm
Tue Oct 09 2012, 15:47

TAIWANESE CHIP SHOP TSMC has announced its support of 20nm chip fabrication as part of its Open Innovation Platform (OIP) by revealing two reference flows.

TSMC has been busy trying to meet customer demand for its leading edge 28nm process node, but as fab rivals Globalfoundries and Intel are moving to sub 20nm process nodes the firm has announced developments for its own 20nm process node. The firm said its 20nm chip on wafer on substrate (COWOS) foundry-first process node has now produced two reference flows, showing the way for chip designers to implement designs to make use of its processes.

According to TSMC, its 20nm process node allows the use of double patterning technology, while COWOS allows for multi-die integration for increased bandwidth to support die-stacking. The firm was keen to stress that existing electronic design automation tools can used with its latest 20nm process node.

Cliff Hou, VP of research and development at TSMC said, "These Reference Flows give designers access to TSMC's advanced 20nm and COWOS technologies. Delivering advanced silicon and manufacturing technologies as early and completely as possible to our customers is a chief goal for TSMC and its OIP design ecosystem partners."

TSMC said its reference flows should help chip designers with the adoption of its 20nm process node, which TSMC has yet to announce for volume production. µ


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