CHIPMAKER Intel revealed some architectural details of its upcoming Xeon Phi accelerator at the Hotchips conference, saying that the chip will feature 512-bit SIMD units.
Intel's Xeon Phi accelerator board was shown off as a working demonstration at the International Supercomputing Conference in June and now the firm has revealed a few more architectural details at the Hotchips conference. The firm said each of the 50-plus cores will feature 512KB of Level 2 cache and a 512-bit SIMD architecture.
Intel senior product engineer George Chrysos reiterated what the firm had said previously, that each Xeon Phi core will not be particularly fast in comparison to the firm's Xeon processor cores, but that the accelerator is designed to divide up workloads and spread them over dozens of cores. Chrysos said Xeon Phi cores are not only physically smaller than Xeon cores but do less prediction, and confirmed that the Xeon Phi accelerator chip is optimised for high performance computing (HPC) workloads.
Chrysos also said the Xeon Phi accelerator has a new interconnect and memory subsystem. He confirmed that the on-die interconnect between the cores is based on a ring topology, and is the same topology used to connect it up to GDDR5 controllers.
At ISC, Intel told The INQUIRER that it will have Xeon Phi boards out by the end of the year and that it eventually is going to put the architecture, which it said was "inspired by Larrabee", into processors.
Intel's Xeon Phi accelerator could hold some clues as to where the firm is going with interconnect between cores in Xeon processors. As Intel, AMD, IBM and every other chip designer puts more cores onto a die, feeding them with data becomes more and more of a challenge. However Chrysos' admission that Intel is optimising the Xeon Phi for the HPC market could mean that hosting companies wanting to offer 50 virtual machines on a Xeon Phi board could be bitterly disappointed. µ
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