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Intel suggests stacking DRAM chips to boost bandwidth

Piles on the chips
Wed Oct 12 2011, 13:45

CHIPMAKER Intel has said that the cost of getting data to processors is too high.

Steve Pawlowski, an Intel senior fellow said, "Scaling DRAM is a problem", referring to the firm's ability to hit its high performance computing goals, adding, "DRAM performance hasn't gone up much." Earlier Pawlowski said that I/O to the processor has become a big issue and he claimed that DRAM manufacturers can expect problems as they move below 17nm.

Pawlowski said, "Beyond 17nm there are problems. DRAM manufacturers need to go more exotic [for solutions]", and suggested that chip stacking might be required. He also added, "increasing memory channels won't work", saying that there are physical pin limitations.

While Pawlowski's mooted solution of chip stacking isn't new, he did mention that it contains several research problems before it can be deployed. A big issue is cooling the lower layers, with Pawlowski giving an example of a experimental multi-layer chip the firm had mocked up in its labs that had its lowest layer melting due to insufficient heat dissipation.

Pawlowski also mentioned the idea of stacking multiple types of chips, suggesting that Intel could put DRAM chips underneath CPU cores, however once again he mentioned that heat could be an issue, saying, "DRAM still produces a considerable amount of heat."

Samsung, Hynix, Micron and other DRAM manufacturers will have to work closely with chip designers if Pawlowski's vision of integrating DRAM into the same die as the CPU becomes reality. The problem is, should DRAM and processor coupling becoming tighter, then customer choice among vendors could be severely limited.

Much like Pawlowski's claim that Intel will have look elsewhere for performance improvements needed to hit exascale performance, DRAM vendors will either have to saddle up with chip designers or spend big bucks looking at new ways to keep feeding faster processors with data. µ


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