CHIPMAKER Intel has announced its second generation hybrid core technology codenamed 'Knights Corner'.
Knights Corner is Intel's second chip in its Many Integrated Core (MIC) chip line and will feature Xeon X86 cores and more than 50 GPGPU cores loosely based on what was previously known as Larrabee. Knights Corner will be fabricated using Intel's 22nm tri-gate process node beginning in 2012, though the firm would not be drawn on the exact core count at this time.
Chipzilla's launched its first generation MIC chip codenamed Knights Ferry at last year's International Supercomputer Conference (ISC), and the firm claims that it will have about 100 customers by the end of 2011. Knights Corner on the other hand, is the company's big hope in high performance computing (HPC) to stop the march of AMD and Nvidia with their respective GPGPU chips and cards.
Nvidia in particular has built a name for itself in the HPC arena in a relatively short time, and Intel was quick to promote the virtues of scalar processors. Intel said that "scalar architectures are needed for HPC" and that Knights Corner is "extending IA [Intel Architecture/x86] to take into account MIC". Both AMD and Nvidia use only single instruction, multiple data vector processing units to make their push into exascale computing, though AMD's Opteron accelerated processor unit (APU) chip coming out in 2012 looks set to compete with Knights Corner.
Intel's big selling point for its MIC architecture is its relative ease of coding, with little modification of x86 scalar code needed to make use of its vector units. Intel went to great lengths to show how simple pragma changes in code have resulted in outfits such as CERN experiencing orders of magnitude speedups.
While Intel was promoting scalar processors, or more accurately the relevance of scalar processors in HPC, the firm made the surprising admission that its MIC architecture is needed to exceed Moore's Law, something that it thinks is required in the HPC world. Intel said that Moore's Law could provide it with a 40X speed up but with MIC architecture it expects a 500X speedup within eight years. That it claims will be enough for MIC chips to hit exaflops scale.
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