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ARM releases a cache coherency specification for multi-core chips

Keeps cores from being fed bad data
Mon Jun 06 2011, 17:53

CHIP DESIGNER ARM has announced its latest AMBA 4 interface and protocol specification for cache coherency.

ARM's architecture is the basis for chips used in smartphones and tablets and with multi-core chips becoming increasing common in those markets managing cache coherency between cores is absolutely vital in order to retain data consistency. The AMBA interface is used by the majority of embedded chip design firms as the on-chip interconnect technology.

With AMBA 4, ARM brings in AXI Coherency Extensions (ACE), which allow for systel level cache coherence. ARM says that having a standard for cache coherency will "reduce software cache maintenance, saving processor cycles and reducing external memory accesses". It's a message that was repeated by some of the largest chip vendors in the industry.

Hongyi Chen, Marvell's VP of engineering in processor design said, "A key benefit of AMBA4 ACE is the provision of a development ecosystem with a standard protocol that makes future hardware design far easier. This protocol enables transparent management of cache coherency that removes a significant burden from software engineers."

ARM said that AMBA 4 is designed specifically to address the computing that's done in mobile devices. It claims that effective hardware coherency is important because it can decrease 'chip memory traffic' and software cache maintenance, all of which saves processor cycles. That in turn helps to preserve battery life or obtain better application performance.

All of this goes to show that while having multi-core chips in the latest smartphones is good for the end-user, designers have to work harder than ever to efficiently use the more complicated hardware at their disposal if they want to preserve battery life. µ

 

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