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Planar transistors are given a new lease on life by ex-ATI boss
CHIP DESIGN OUTFIT Suvolta released its Powershrink CMOS transistor technology that it claims will reduce the power consumption of CMOS circuits.
Suvolta, which has ex-ATI CEO David Orton as one of its directors, has been working on process technologies that will allow chip manufacturers to reduce current leakage without any significant decrease in performance. The firm's Powershrink technology uses Deeply Depleted Channel (DDC) CMOS transistors and DDC-optimised circuits and design techniques.
According to Suvolta, the use of DDC allows chipmakers to reduce power supply voltages by up to 30 per cent and reduce power leakage by 80 per cent. Most importantly, DDC technology can be used in the fabrication of CPUs and system-on-chip packages built for use in smartphones and tablets.
Suvolta's DDC technology has been picked up by Fujitsu for its 65nm process node. 65nm is almost prehistoric when you consider that Intel showed off its 22nm Tri-gate transistor technology in May. However Suvolta claims that the leakage on its 65nm process node is less than that of Intel's 45nm process node. That's an impressive claim that will no doubt be put to the test as chip firms will want to get away with lower fab costs.
Suvolta was keen to stress the ease with which firms can adopt DDC technology. After all it's no use if the cost of implementing DDC offsets any yield gains. To that end, Suvolta said that its DDC technology does not require new equipment or materials in fabs and uses standard design tools and flows.
Bruce McWilliams, president and CEO of SuVolta said, "Lowering semiconductor power consumption has far reaching benefits for the range of applications and products that can be developed. Suvolta is very pleased to be providing the industry with a technology platform that is advancing the possibilities from continued scaling of planar, bulk CMOS technology."
McWilliams' mention of planar CMOS technology is a reference to Intel's announcement that it will use '3D' transistors for its 22nm process node. In making that announcement, Intel said that it could not move to 22nm without it, sounding the death knell for traditional '2D' planar transistors.
Power consumption has always been the fundamental limiting factor in processor design. It's a constraint that affects how fast a processor can run and it ultimately decides whether it is viable to fab a particular chip. Reducing the power consumption of chips can be achieved by two methods, either redesigning the architecture or improving manufacturing techniques.
Since architectures remain fairly stable over decades, it's up to process engineers to step up and enable chip designers and fabs to produce viable chips. Suvolta hopes to cash in on chip designers and fabs that want to squeeze every last penny of revenue from well established process nodes. µ
Tags: Hardware
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What's not to like George?
The fact that 3D technology requires you to change FABs AND the fact that the yields are horrible AND the fact that only Intel has it at this point.
"Even chip designers don't like 3D much"
Really ? That's like saying race car drivers don't like Ferraris much. All chip designers would love having 3D FinFETs in their toolbox. Higher performance, lower power, smaller size. What's not to like ?
So this is a modern incarnation of the old Back Bias days in the late '70s. I saw it first when I was at National Semiconductor and all the Nmos design engineers used this technique in their designs. They would bond out the VBB pin and play with different voltages to find the optimum value. Later, they stopped using an external VBB pin and designed in internal charge pumps. The industry went away from this technique decades ago. It'll be interesting to see what's different with the new technique. Since their CTO was an Intel Fellow until 2009, I suspect Intel was well aware of this idea when they went ahead with 3D.
Because of transistor variation Fabs need to make a change at the 22nm node to continue scaling. Everyone is considering using FinFET's or Fully Depleted (very thin) SOI. With FDSOI you transfer the processing problem to the wafer vendor (hence Soitec's excitement with the tech) and pick up an Rext problem no one has demonstrated a solution for yet (see http://wenku.baidu.com/view/0d8e057831b765ce050814a5.html slides 45-58). With FinFET's you keep the processing problems in the Fab.
One really cool aspect of FDSOI is the excellent response it has to Body Bias. BB is lowering the operating voltage (Vth) of the chip by adjusting the voltage of the transistor substrate. This can dramatically reduce power consumption in FDSOI if you can get it to work.
Since Suvolta is not a Fab they can't really produce a process technology to reduce power. Rather, they are re-introducing the well known technique of BB to reduce power. This is a design technique (since they are a design company) not a process technology and it is not a power free-be. It costs layout space (because you have to make multiple contacts to the substrate) and can reduce speed, especially if you are trying to reduce both active and passive power (they take opposite BB voltages that require switching in a large volume of Si). However, if you are a small design house it is a good option because it becomes easier to tune speed paths without changing the processing of the chip.
It is very deceptive to claim to be able to achieve the same performance on the 65nm node as the 45nm node by just introducing BB. You may be able to match the leakage from one node to the next but you will pay a performance penalty on the 65nm node and be even farther away from the 45nm node than before BB. There is no substitute for scaling. If so everyone would do it. BB has been around for a long time.
BB becomes more interesting with FDSOI since there is such a small volume of Si the BB must switch. In FDSOI the extremely thin BOX allows the substrate to be much more closely coupled to channel. This eliminates many of the disadvantages of BB (see the link above). If Suvolta was talking about this it might be something more interesting than a marketing tactic dressed up as a new technology. But, they did get the pseudo-technical press to provide them with free ink.