Toshiba claims massive energy savings on flip-flop circuits

A WHOPPING 77 PER CENT less power is needed for Toshiba's 40nm scale CMOS flip-flop circuit compared to earlier flip-flops, the Japanese company claims.

A flip-flop is a circuit that temporarily stores one bit of data during arithmetic processing by a system-on-a-chip (SoC). For SoCs, Toshiba explains, flip-flops are essential and such processor systems have 100,000 to 10 million of them.

To make the power savings Toshiba eliminated the flip-flop's clock buffer. The clock buffer has been used to produce a clock inverted signal required for the circuit's operation. Signals from the processor's actual clock cause the clock buffer to consume power even when there is no data change.

Previously to reduce this power consumption clock gating has been used to stop the signal from getting to some buffers that were not going to be changing data.

So, Toshiba opted for just getting rid of the buffer while cleverly still getting the flip-flop circuit to work. To make it work Toshiba said it added "adaptive coupling" to the flip-flop.

Toshiba said, "A combination of an nMOS transistor and a pMOS transistor, this circuitry adaptively weakens state-retention coupling and prevents [data] collisions." µ