AS IDF SAN FRANCISCO 2010 draws near, we can’t help but feel the eagerness to see how the latest “Tock”, Sandy Bridge, will perform with the new AVX instruction set.
Back in the Spring of 2008, Intel disclosed the development of a new instruction set, a superset of SSE and the successor to SSE 4.2 that introduces 12 new instructions - AVX.
The new set increases the size of SIMD vector registers from 128-bit to 256-bit, adds 12 new instructions as well as allowing instructions to have three operands instead of just two. This actually means that code execution efficiency should go up a bit, as well as providing some nifty floating-point juggling that will accelerate multimedia operations considerably, according to Intel. AVX is also said to cater to CPU parallelism and power efficiency - two driving forces of today's CPU development. Increasing the scalability of parallel computing apps – something that will definitely appeal to the HPC crowd.
Sandy Bridge, which will make its debut at IDF San Francisco 2010, will be the first processor in Intel’s ranks to feature the instruction set, and it will almost certainly stretch its legs during the event. Through the use of AVX instructions, the peak GFLOPS throughput is said to increase to 32 double-precision GFLOPS per core on Sandy Bridge processors. OS support, of course, is also vital to get this instruction set to work, so as long as you'll be using Windows 7 SP1 or later, that is, about the same time as Intel launches Sandy Bridge, you'll be good to go.
If you’re in the software optimisation business you might be tempted to drop by IDF to see how you can get that old SSE code running as new AVX instructions. µ