Intel plans supercomputer coprocessor

CHIPMAKER Intel plans to extend its presence in the supercomputer market with multicore 64-bit processors configured as co-processors.

Intel told the world plus dog at the International Super Computing conference in Hamburg that it has a cunning plan to replace lots of standard Xeon processors commonly used in massively parallel supercomputers with many-cored system-on-chip (SoC) processors.

Kirk Skaugen, general manager of Intel's data center group announced what Intel calls its Many Integrated Core architecture, or MIC (pronounced 'mike').

MIC chips will be put into HPC systems as co-processors. If this sounds familiar it is just like what Nvidia is doing with Tesla GPUs and AMD is doing with Stream GPUs.

There are similarities between the MIC chips and Larrabee, a GPGPU project that Intel apparently has abandoned. Larrabee used a superscalar x86 64-bit core and a 512-bit vector math unit. Larrabee also had a very wide ring bus for linking all of the cores and the caches together, which is a big part of MIC's design.

Skaugen said the MIC chip family will be known as Knights, and showed off the "Knights Ferry" coprocessor. It has 32 cores, Skaugen divulged, running at 1.2GHz, and it has four execution threads on each core for a total of 128 threads per chip.

The chip has 8MB of shared coherent cache and 1GB or 2GB of GDDR5 graphics memory for munching numbers. µ