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Samsung builds world’s first 20nm semiconductor chips
KOREAN CONGLOMERATE Samsung is crowing about being the first in the semiconductor industry to produce 20nm class NAND flash memory chips.
The chips will be used in Secure Digital (SD) memory and embedded memory solutions. First off Samsung will introduce 32GB MLC (multi-level cell) NAND flash memory with the 20nm class chips.
Later on memory cards should be available from 4GB to 64GB. This announcement comes only a year after the company started producing 30nm class NAND flash memory chips, and Samsung noted that 20nm class chips have 50 per cent higher productivity.
Write performance is also faster for 20nm class NAND flash memory chips, as an 8GB SD high density card based on them is 30 per cent faster than one based on 30nm class NAND flash chips.
This will increase the range of options when it comes to memory cards for use in new technology such as smartphones, as well as for high-end IT applications. Samsung also claimed that it has made its 20nm chips just as reliable as its older ones.
What this means for users is that less expensive and better performing NAND flash memory chips will be coming to market. µ
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The clue was in the phrase "... on a two-dimensional die ...".
@ChemC - thanks. I guess there is more to it than component density. Or maybe the Samsung marketing guy can't to maths either.
It is not 50%. As mentioned by richard, it is a 2d chip, idealized as a square. At 30nm, each 'side' is 30nm, for 900nm^2 per transistor. At 20nm, each 'side' is 20nm, for 400nm^2 transistors. And 900/400 = 2.25 = 225% (of the original, so, 125% improvement).
ChemC
Ok lets do a maths 101.
(new value / old value) x 100
(30 / 20) x 100 = 150
The difference being 150 - 100 = 50% difference.
How is it 9/4?
It is actually 9/6, 12/8, 15/10, 18/12 etc etc.
THAT is how it is 50%.
Although vague, I assume that the article means that the yields are much lower on the 20nm process, but still yields 50% usable dies/wafer.
You are correct that ideally 20nm would be 9/4, 125% more dies/wafer than 30nm.
So, at 100% efficiency at 30nm and 100 dies/wafer, 150 dies would need to be harvested from the 225 dies in a 20nm wafer, 150/225 = 67%.
So, more wasted dies, but more dies/wafer, a net gain for our fair city!
ChemC
Samsung is trying to misleading people, 20 nm class could be anywhere between 20 to 30 nm as they are behind IMFT (Intel/Micron duo) in developing under-30nm NAND.
Any bright spark tell me why 20nm is only 50% more productive than 30nm on a two-dimensional die. Surely, it is 9/4 times (125%) better?