Tilera releases a 100 core processor
TILERA HAS ANNOUNCED a new family of four processors, which includes one it claims is the first with 100 cores.
The TILE-Gx family includes the TILE-Gx100 which has 100 cores - more than you can shake a stick at - and claims to offer the highest performance of any microprocessor yet announced by a factor of four. The company says it is available with 16, 36, 64 and 100 cores.
Tilera claims the TILE-Gx range is low on the juice, taking performance-per-watt to new levels with ten times better compute efficiency compared to Intel's next generation Westmere chips.
According to the outfit, it simplified everything by devising its own Multicore Development Environment.
This environment is based around a two-dimensional Imesh interconnect, which eliminates the need for an on-chip bus, and a Dynamic Distributed Cache system allows each core's local cache to be shared coherently across the entire chip.
It apparently means that the chip's performance can scale linearly with the number of cores on the chip.
The TILE-Gx processor family, fabricated using TSMC's 40nm process, operates at up to 1.5GHz with power consumption ranging from 10W to 55W.
No word on pricing yet. µ
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emm.... looks tasty, but what it's good for..
One thing I could think is lot's of VMs on one Server.Also Folding@home could benefit (sarkasm)
Read the "Applications" section...
http://www.tilera.com/products/TILE-Gx.php
It's not x86, so we won't be seeing one on a desktop or laptop. Would have been nice if the author noted it wasn'tx86 and saved me some time.
One of it's listed features is H.264 HD encoding. I wasn't aware that HD required that much power. It looks like these will be aimed at cloud computing data centers and Telecoms.
Think of the databases that thing could crunch.
Think about anything these would do clustered in a cloud.... :::Drool:::
Oracle power hungry?? It's heard of it...
I don't know. I suppose it depends on a decision rendered by a panel of judges as opposed to a spot on the ball, itself. The right to play games of skill, however, should itself, be processor-inalienable.
Run off-the-shelf C and C++ programs
in 64 bytes - the chips could serve as co-processors alongside x86 chips.
But who are going to do the takeaways?
we can't boil the ocean.
Are these fare?
for the all-you-can-eat
BOGO crowd?
grab a plate,
help yourself,
help yourself again
Situation vacant for the right wait staff - apply wit end
LOL. While I understand your question, what did you smoke for lunch dude?!? LMAo. Nice reply.
Same Story, just few bits deeper in Tech Facts.
http://www.tgdaily.com/content/view/44417/135/
Basicly, Little CPU Useometer goes higher faster with less cores. Will 100 Cores Sing:"Yankee' Doodle Dandy"? In 4 Part harmony.
drashek
If you want to render a few scenes for the next animated/heavy CG effects movie, maybe you'll want a few of these. Or not, a few benchmarks are in order.
1) No FPU. You're not going to be doing rendering with this chip. Obviously only a problem if you actually need a FPU, so shuffling packets around is fine.
2) 2D grid interconnect. The only good thing about a 2D grid is that it's easy to make the hardware. This cascades on to cache coherency issues. You really, really don't want the chips in the top left and the bottom right stepping on each others' feet.
Basically, the chip does well for managing streams of data. If you treat it like 100 independent computers and take a dataflow programming approach (and don't need a FPU), it works well. But you really can't compare it to a more general-purpose CPU like Westmere.
Arm processors out sell x86s aready. And they vary from 16MHz with no FPGA to 1.5GHz with Vector FPU. The fact of the matter is floating point predates FPUs. It's just a data structure and the majority of CPU cycle aren't typically spend on Floating Point Processing anyway. This type of architecture supports a "Software Pipelining" programming model which is basically taking hardware concepts and implementing them in software. This a more general purpose architecture than Vertex or Pixel Shaders and allows Wide and pipeline parallelism. x86 has too much baggage to scale well, to put multiple cores in a single chip the cores MUST be as small as possible to increase the ratio of "active processing" to wasted wafer. Most the arguments against this architure could have been applied to what is currently the most successful CPU on the market, the ARM. (PCs aren't the largest market for processors.)
Chuck Moore (of Forth fame) has been busy developing multi-core Minimum Instruction Set computers for a while now. Current development has him testing 4 and 40 core chips with a 144 core chip close to production. See:
http://www.greenarraychips.com/home/products/index.html
All chips are based on a minimal Forth type instruction set similar to his colorforth language and run at very low power levels. Simple design that gets around some of the issues of parallel processing.
See also: http://www.colorforth.com