- Saturday, 21 November 2009
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He is drinking from the INQwell when he should be drinking beer - Anonymiser
IBM POWER7 details emerge
THIS WEEK'S Hot Chips conference saw the first serious talk about the IBM POWER7 processor, the monster square-inch sized 45nm 8-core chip with 4-thread simultaneous multi-threading (SMT) per core.
It's coming out a whole eight years after the previous 4-thread multi-threaded general purpose CPU, the Alpha 21464 EV8, was announced but prematurely killed.
The new IBM processor also has wider per-core execution at 6 ops per cycle (the Alpha was designed for 8 ops per cycle in 2000, though), a whopping 32MB shared eDRAM L3 cache on chip fed by 100 GBps dual 2-channel DDR3 controllers and 360 GBps inter-CPU fabric. It even has Turbo Mode and Power Gates just like on Intel's Nehalem. And all that is scheduled to run at 4GHz, if IBM doesn't break its promises.
IBM Power6 wasn't that old either, and in its 'plus' iteration it reached into the 5GHz realm. Yes, it was inefficient in Linpack and similar benchmarks for HPC - roughly 60 per cent achievable out of theoretical peak is really bad for a modern CPU - but it was the 'speed racer' record holder of all time.
Why did IBM make such a sudden change from Power6 to POWER7, aside from getting a massive performance gain?
Note the branding change from Power6 to POWER7 (all caps). According to sources, this had something to do with the PowerPC co-branding with Apple and expected acceptance of Power6 derivatives into the Apple PowerMac line a few years ago, before holy Steve Jobs made his about-face to kiss the hand of Miss La Intella. Remember that Power6 included full AltiVec support, needed for the MacOS but not exactly beneficial for IBM's AIX environment.
Interesting derivatives in the Power6 roadmap included entries such as Power6L ('L' as in light) and Power6UL ('UL' as in ultra light), nice matches for the Mac Pro and Imac lines respectively.
Of course, IBM did hit the thermal wall with the high-GHz Power6, just like before it Intel hit the wall with the Prescott flavour of the Pentium 4. Intel then changed the landscale, and bagged Apple away from IBM with Core 2, and IBM was left to rehash the effort.
That's the inside background of the new chip. More on its detailed works next week. µ
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SMT stands for 'Simultaneous Multi-Threading'
- not 'Symmetric'
(because that describes what it is quite well)
Its nice stuff above, about kantner, if you look closely, hasn't posted anything in year, obviouly another Mike'd Out. Use to post in MAD AMD MAME.MD log, 2.
However, sure ibm be super, yet BULLDOZER Is Rumour'd to have 4 Channels of DDR3 1333. Thats Lots better & 12 cores 2x6., when finds home, where Buffaloe rhoame, ^.+.^ deer/Antleope Play, inside MAGNY Core. Its rumour from Last Day of HOT CHIPS 21. N.B.
NOTE: Please do NOT discuss the Shattered Horizon Beta outside of these forums, thanks!
Especially after Your System Shatters.
From 200 to 400 took 10 years to 500 another 10 then 15 years to 6 now 7. Ole Lucky 7. Yet Beta of 11 is being developed. it delivers A&W Root Beer Floats , Calif Burger RAW onion & TOMATOE with Potato Crinkle Fries & thousand island dressing.
DRASHEK
Thanks Phil, yes I meant Simultaneous (not Symmetric) but the automatic acronym expansion engine got it wrong. Anyway, I'd love IBM to have an option to disable SMT for HPC jobs anyway.
I wonder what kind of heat output this thing generates, does it need water cooling? When will IBM step back into making x86 chips? I want to see a Core ibm7 Blue Lightning lol
IBM is clean on holding to their three-year plans. Nothing got rushed here. That it is a densely-cored, densely-threaded, throttled-back GHz machine wasn't completely clear until a few months ago. The three year plan did say something about socket-sharing with AMD and possibly Mainframe-instruction-set capability. Whoever gets more on this, I am interested!
Why wouldn't IBM take an advantage from the alliance with AMD if they really want to make their way into x86 systems. You've done that with Roadrunner (Opteron+Cell Broadband) then why not Opteron+POWER7? I know it would be hard to do so but hey, you're IBM! You mentioned about making chip from virus or whatever. If you can do that, by using Torrenza platform, this should be easy for you.
You know, you're right, this processor fits the specs for a DDR3 Magny-Cours socket.
Mangy-Cours is 2x dual DDR2 and 360Gbps inter-socket connect, isn't that HTT 3.1? Although I thought that theoretical max throughput was north of 50GB/s which is over 360Gbps; 400Gbps or greater actually.
I heard rumors a few years back that said IBM was going to use the Opteron Socket "of the future."
Maybe they will share G34.
I am curious about the "100 GBps". Is that suppose to be 100 Gbit/s or 100 GB/s? I have seen so much shit here like Kbps, mbps and all that nonsense. Quite frankly, I cannot believe anything you write. Have you ever tried to find a job as janitor?
"Moving on after the Power(Mac)6"
Power6 has nothing to do with Mac. At one point the G5 CPU was a cut-down, simplified version of a Power4 but that was a LONG time ago.
"Note the branding change from Power6 to POWER7 (all caps)."
It's always been POWER (it's an acronym). If you Google presentations on the earlier chips you'll clearly see POWER4, POWER5, POWER6, etc. People simply don't like writing in all caps so you usually see it written as Power.
It's a good point but I don't think there are many systems out there that have 100GBps memory bandwidth to a single processor. 100Gbps is actually provided by dual channel RAM at 800MHz, so, I would expect the quad channel arrangement with DDR3 to give at least 270Gbps (1066MHz), if not more like 333Gbps (1333MHz).
"Thanks Phil, yes I meant Simultaneous (not Symmetric) but the automatic acronym expansion engine got it wrong. Anyway, I'd love IBM to have an option to disable SMT for HPC jobs anyway."
This is possible. There is a command in AIX called smtctl to do it. It has been there since power5.