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Soitec and Big Blue go 3D
SOITEC is one of the movers and shakers at Semicon West this year, announcing it will collaborate with Big Blue to provide wafer thinning and bonding services to IBM. Soitec, the big daddy of silicon on insulator (SOI) substrates, is hedging its bets on next-generation 3D chip development with Big Blue at the 22nm semiconductor technology generation and below.
While still somewhat of a market niche, SOI has enjoyed success with IBM’s chip division, and with AMD, over the past few years. But pundits expect the 22nm node to present challenges for SOI technology, and the use of 3D chip technology is one option to continue the push to scale down to smaller process sizes. This has to be good news for companies like AMD who rely on SOI for their CPUs, although one has to wonder how long until the firm moves to a bulk process considering Global Foundries will be able to offer littler chipper either one in the future.
3D chip technology doesn't lack for hype, and the boffins at IBM apparently see it as having huge potential to solve a number of problems which have been challenging chip designers hungry for more performance and less power at advanced process nodes.
3D chips layer one chip on top of another using a technique called wafer bonding, and this is where Soitec comes in. IBM's technique uses one base layer of silicon with active wafers layered on top. This allows engineers to place a processor on the bottom of the stack and then layer memory or other components across the top, resulting in a thousand-fold decrease in connector length, as chips are no longer organised in 2D layouts with wires connecting transistors at the outer layers of the chips. This reduces the distance data has to travel, resulting in much faster processing capabilities.
But how fast this technology will make it to market still remains to be seen. µ
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The problem with 3d chip design has always been heat dissipation.
In 2d chips you can cover either side with a heat sink or any form of heat conduction and that works well.
With a 3d chip, you basically get a N-1 layers of chip which are not cooled.
Solve this, and you get a MASSIVE parallel chip.
Go IBM!
PS: I work for IBM :)
The first thing that comes to mind when reading this article is heat. You're sandwiching everything together and the top layer (in a 2-layer design) effectively becomes the heat conducting medium for the bottom layer to the heatsink. Not good, and that's only with 2 layers. What if we have, say, 5 layers?
The other thing is M-Space. Is this what AMD is planning? The feature of 3D chip design is that you shorten circuit paths. Take for example the Athlon design. The Load/Store units and the Bus Interface units are located on opposite sides of the chip. I would expect these two parts to talk a lot with each other. In a 2D chip design signals have to travel all the way across the chip to reach the other unit. In a 3D chip design you can place the L/S units directly above or below the bus unit, thereby shortening trace lengths and reducing heat. This way, I would expect a 3D version of the Athlon (or any other chip) to become thicker but occupy less die space. I think the most important thing here is the material used.
I fully expect as we try to stack more and more layers well see columns of insulated metal or other heat-conducting material put down through holes in the actual silicon to pull heat away and deliver it to the heatsink. It may even be beneficial to have channels of material directing heat off to the side, then up. This will become another logistical puzzle in wiring around the columns while at a minimum cost to speed.