INDEPENDENT BELGIUM-BASED research group IMEC claims to have achieved breakthroughs in scaling chip technology to the 22nm generation and beyond.
Working with such 800 pound gorillas as Fabzilla (TSMC), Chipzilla, ST, Qualcomm and Sony, amongst others, the IMEC crew has reported a successful integration of the laser-anneal technique in a high-K metal-gate process and a step towards manufacturing aggressively scaled germanium-pFET transistors.
To scale chip technology to the tiny 22nm node and below, materials like high-k metal gates are considered to be the best options available. One integration scheme the IMEC team is working on involves metal inserted poly-silicon (MIPS). With MIPS in the process mix, IMEC has compared spike anneal and laser anneal.
Also, for the first time, IMEC has shown functional ring oscillators - a device composed of an odd number of logic gates whose output oscillates between two voltage levels - using the laser anneal process. If this process ever hits production it could reap huge benefits in thermal budgets - that is, leakage - which we're sure our friends at Fabzilla will appreciate based on their recent hang-ups at 40nm.
Another scaling option that IMEC outlined was the use of high-mobility materials such as Germanium to boost the carrier mobility of MOS transistors. Adding new materials has the potential to pump higher drive currents and increase performance at the 22nm node and beyond, but the industry is facing some significant challenges at the 22nm generation.
It's looking like collaboration will be king when it comes to satisfying our insatiable appetite for higher and higher chip density in 2012 and beyond. µ
Charlie writted article yesterday from SF Developers forum, where 12 nm was displayed. here:
http://www.semiaccurate.com/2009/07/15/imprint-lithography-stamps-out-chips/
It uses laser & use 1 sec cool down as device etchs or prints image onto glass substrate & Resist, then washes away unlasered area. Its Fruit Basket World.
vondrashek
Drashek just made sense!
Well apart from the fruit basket.
Drashek always makes sense - you just have to read better.
Sorry, you have serious problems if you are making sense of all Drashek's writings....
Either Drashek's a bot and his software has been majorly improved, or a translation program somewhere has itself been majorly improved.
If fact thermal budget refers to the total amount of heat (ÂșC*processing time at each fabrication step). Thermal budget must be kept as low as posible to avoid dopant diffusion, ...
(Current) Leakage is related to the device/circuit when biased, nothing to do with processing but with geometry/topology at the device level.
I think this guy's just trying to sound cool. Get a life, dude.