INTEL LAUNCHED NEHALEM a few months ago, and it caught up with everything else on the market and then some. The only problem was it only went to two sockets, but as of today, that is no longer the case.
Today, Intel is talking about, but not launching, the Nehalem EX CPUs, the four socket version of Nehalem. If you were overly cynical, you would say that the chip isn't available until Q4, so why talk about it now? Well, AMD is rumored to be launching Istanbul at Computex in a week or so, and Intel needs to counter the buzz.
That said, when you can buy the EX later this year, it will likely dominate the four socket (4S) segment of the x86 server market. Nehalem was a monster with four cores and 8MB of cache, think about what this chip will do with eight cores and 24MB of cache. Toss in four CSI/QPI links, and you have something that will scale to pretty high socket counts.
Not that complex, right?
Add four memory controllers to that instead of Nehalem's three, and you can have 16 DIMMs per channel, 64 per system. One interesting thing is the use of buffers on the mobo, not on the DIMM. We told you about the microbuffer concept two years ago, and now it is out. This means instead of expensive DIMMs, you have expensive mobos, but when you are talking 4S+ machines, nothing is cheap.
Intel dumped a lot of RAS features along with FB-DIMMs, and hopefully it is bringing a few back with the microbuffers. Time will tell, as details are scarce for now.
This one is complex
If you think the 4S servers are complex, take a look at the 8S ones. The above diagram is an 8S 64 core 128 thread machine that should support 128 DIMMs per box. Throw in a few 32G Metaram DIMMs that should be out at the same time the 8S boxes are, and you can put 4TB of RAM in the box.
IBM laid out the numbers first with a TPC-C benchmark of 1.2 million, the first x86 box to break that barrier. Intel and IBM are claiming tons of other benchmark wins across just about anything that is relevant for the 4S server market.
The box IBM uses for this is called eX4, the fourth generation of IBM's X-Architecture. For those who don't follow the enterprise multi-socket server market, this is the PR approved way of saying IBM is making a chipset. The next one, eX5, is in testing, and IBM promises it will be out in 'about a year'.
One of the most limiting things for x86 in the high end, mainframe-like big tin marketplace is the error correction features, basically RAS. Intel has been artificially limiting x86 RAS features to protect its Itanium market, but now Intel is bringing in MCA, Machine Check Architecture, to Nehalem-EX.
MCA basically detects errors on the CPU, memory or I/O, and allows them to be corrected without crashing the whole box. This needs OS support to work right, and Intel has Novell, Redhat, VMware and Microsoft on board to enable MCA. At least on Windows, we are told it will mean over 17 times the uptime for boxes hijacked by eastern European spammers.
All in all, Nehalem EX is about what we expected it to be: eight cores, more cache, all the Nehalem goodies, more scalability and more RAS. If MCA gains back what Intel lost with FB-DIMMs, there doesn't really seem to be a down side here. µ
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