Intel word of the day

I could have recycled Wackypedia as well

http://en.wikipedia.org/wiki/Intel_Haswell_(microarchitecture)

Eight is Nice Core Number, yet 12 seems to be Clincher. Well with 8, like cell you might have add-on controller, yet that ONE Controller has to Parse its instructions to every core, waste of time & each core is more less stuck with one controller for all. In dual core with one controller times four sets, each set has its own special abilities & instructions don't have to wait for 7 other cores to roll by, its just much faster & uses second core to avoid freeze & parse work simply, in one two lock step. Will there ever be 12 core with 4 controllers & 9 cores. Maybe not, especially 22 Nm is near bottom end, No further size reductions, perhaps. those four dual processor units can squirm & reply much more instantly, have less cross talk & once task is learned, set up tasks faster & more accurately. TS Drashek

One last insight, No Matter Cores & controllers each task only uses one controllers & one core set. so multi controllers add lot of singularity to spe4cfic mosh. if its fast, whole controller & cores are fast, leaving others to their own needs. yet there is NO actual difference in How instructions are handled, one controller to one set of cores.We can assume speed Up by thinking how Playstation3 is bit on slow. instead of ball, pitcher & catcher, you could add plenty of sneering Fans, goodyear Blimp Gas Bombs & Field riot by having quicker control of entire processor. STeWie Drashek

wow - i resolved not to comment on Drashek but this s**t rocks once more - such entertainment he offers through his effort to produce drivel. Bet he's never sat in a pub in SOHO with Charlie mulling over images of engineering reference dual dothans like people who do actually make sense ;)

Haswell is really old news, but if you mean they've already manufactured a 22nm chip, that's a really good news. From what I know, 22nm is going to be difficult due to oxide layer getting thinner and a lot of leaks.

Good News, Your ALL Laid Off....Hahahahaaaahhhh. At Any Rate If you had 4 controllers, they would be fed from HDD/DDRX. SO maybe finally that Barcelona 2Way CACHE Crossbar that Larrabee also is dying upon, be Final Fastest, solution. Controller could be switched (What are switches for?)Hahahaaaagggh, from HDD/Memory I/o to Controller W/ Faster Run with L3 2Way Crossbar from Controller to L3 Cache & Back for each controller, Seperately from I/O.Two Controller Inputs Choices.. Once its Fast, Then Parsed nature of One Controller can be Heftly Changed by using L3 cache. Each 1/2 core unit could run at its own pace, with No BackLog into Hdd/memory while one controller rules roost with Long Instructions, NO, 2 Way quickly brings into core needed software without anyuse of HDD Nor Outside memory Slots. From Charlie X orphan to Capt'n Kirk d' Crunch NutBuster. No Longer orphaned to Long Parsed waiting line, core would have much better responses. Old things that happened & dissappeared, as lost in I/O Maze & routing of switches gone, Now become standard fare: increased Potentate. No Longer would controller be feed from outside cpu at ALL times.I/O hits core w? "Printer", then core uses L3 cache 2 way crossbar to see Instructions for "Printer", If None, Then I/O Retrieval. Then Build L3 Cache 2 way Crossbar File for "Printer".etc.Next: Figure Out if Portugese Water Board Would Increase Andrews IQ ZERO. Signed:STeWie Drashek

You mean, like PowerPC had back in, oh, 1993?

These days when I come across an Inq' article comment of a certain length, whose first line consists of inappropriate capitalisations, poor grammar, poor punctuation and general bilge, my gaze immediately skips to the bottom of the comment. Upon seeing a certain name I then skip that comment. Am I alone?

Cache idea was Vacumne tube idea. (Vacumne in Ultra Viloet text), where one programe ran & memory devices had to be Real Time, In actual Useage. Memory being wire or ribbon tape.Cache Being Needed for Comparrison Unit.Then Simple Transistors made Much Smaller Core, however, Probs: Tranistors don't always go to Default State, so Second Core Was Added, Program is run after checking core, like bios, resets every transistor to pristine state of ready.Then /Second Core Runs Program. Guarenteed Successful Operation in Problematic scale. Then IC Chips made scale so small that second core became less Ready State Establisher, although its still needed, today, NOT as Whole Core, Just sub architecture.., however slow main processor was, they behaved like multi language,(MPLS) multi terminal soon enough, colour, too. Radio, TV & Lan ALL State of Art, Delivered to public, Dod & Science, well its capitalist ballfield,(Remember Testing Osilascopes Where 40 Years Ahead in Memory of Test Machines themselves. given cost & secretiveness, its miracle it got to general public at ALL.. Today Power Processor from ibm is in its 6th or 7th Generation & 2 Way Cache Crossbar/Core seems to be part of apha program. Its' NOT that Barcelona Technicians cann't just BUY Manuels & ibm POWER Processor for examination, Thing just Burps Out Its; Guts,As Print Out, Once Public,Its TimeFrame or RoadMap until Retail Incorporation 2 Years+. Yet will they NEVER Get 2 Way Cache CraossBar right? Or Caught Up to Todays' ibm/Chartered Standard. Now is GOOD Time to clean House & Polish Technology into Gaming. I must mean one controller into 3 cores as controllers don't count as ?core, which is right Up My XMP Inventive Experience @GMU. 3 cores times 4 is 12, Hyper Thread/Transport that into 24 Threads & you have Grinder which is ready to play GAMES in 24 bit Hungrily. So theres HINT of Truth to My Poor OLD GREYNESSES,Even if its Not FULl IQ'd OUT. Yet Phisiology of Beast is still ibm/payee Wishes, until its Ultee' Signed:drashek Patent Copyrighted & Marked for Trade. DLLR Level 2 Rm. 220.