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Intel introduces iWindscreenWiper™, iChef™ and iFlexyDesktopMobos™

Desktop Roadmaps Cooking and motorcar notions exceed expectations
Wed Dec 29 2004, 09:55
SOURCES SAID Intel is likely to introduce its 6XX family of desktop processors in week nine of 2005. As we've revealed before, the first processors will be at speeds of between 3GHz to 3.6GHz. The chip giant is hoping to introduce the 3.8GHz version in the second quarter. All these processors have 2MB of level two cache and the chip giant has been busy sampling them since the middle of November.

They also all support iAMD64, or EM64T, as Intel calls 64-32 tech, and hyperthreading. The firm is encouraging its channels to market to sell up the 6XX chips over the 5XX on cache, and on branding, as well as using the XD (execute disable) bit, which AMD describes as the NX bit, and which will stop certain kinds of viral attack.

SSE3 is also being pushed as providing improved multimedia for software applications that can take account of it, while EM64T promises support for future 64-bit applications. The 2MB level two cache will provide better gaming, Intel says.

So what are Flexible Mother Boards (FMBs)? This describes how Intel will provide chipsets that will not only cope with 2MB L2 Pentium 4s but with dual core processors. These are the i955 (Glenwood) and i945 (Lakeport) Express chipsets.

But the tour de force in Intel's plans is its Enhanced Speedstep technology for the family of processors, and we understand that it is providing a motoring analogy to push this idea.

For example, if you imagine the CPU to be a windscreen wiper on a car, and we must admit this hadn't occurred to us, the wiper flicks backwards and forwards at different rates and speeds, which represent power consumption and performance.

No really. On a day when it's drizzling, the wiper moves fast enough to clean the screen of the raindrops - using just enough power to do so. But on a day when it's sheeting it down, the wiper moves faster - that is to say, it uses more power and provides more performance. No really.

Intel reckons that the Smithfield dual core, also supported by Glenwood and Lakeport, builds on its concept of hyperthreading by bunging together a two times 1MB L2 cache, XD, EM64T and WindscreenWiperMarchitecture.

While the x40, the x30 and the x20 will debut in the third quarter, they will use the existing infrastructure of threaded applications. These will be particularly important in digital homes and digital offices, it claims.

How will this work? Intel is inviting its partners to consider dual core microprocessors in the same way you probably understand how your food is cooked in restaurants.

Wot--only-one-pizza-at-a-time-No really. Two chefs - that is to say two CPUs, work on two types of dish using two pans (programs) on two cooking rings. The two chefs can switch two dishes prepared in parallel and switch the contents of the pan over one cooking ring. No really.

This provides the diner not with a hopelessly mixed up dish - for example filet mignon and lemon sole, but with Toad in the Hole and Lancashire Hotpot.

And those, dear readers, are your cooking and motoring lessons of the day. µ

 

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