Pacifica is the new hardware virtualisation hardware from AMD, and early next year, it should start showing up in all Athlon64 and Opteron CPUs. Vanderpool (VT) is the Intel equivalent, and it is discussed in a fair bit of detail in the following articles, parts one, two, three and four. If you are not familiar with hardware virtualisation, please read these articles for background.
First off, let's get the big question out of the way, Pacifica is not directly compatible with Vanderpool in that any program written for VT will not run on a Pacifica CPU. This does not mean that they do not do the same thing in just about the exact same way, they do, but they do not necessarily use the same mnemonics, and have enough differences that they are not binary compatible. I mentioned superset before, and Pacifica is just that. It does what VT does, and adds two very key pieces, both closely linked to the AMD64 architecture. The first one has to do with the memory controller, on chip in AMD64 CPUs, off chip on Intel products, Pacifica adds more modes. The other, the Device Exclusion Vector (DEV), deals with DMA and devices that need direct memory access. Similar functionality is either not present, or not disclosed on VT hardware.
The first part. The added memory modes are one of the places where Pacifica shines. Under VT, you kept each VM in its own space by use of the MMU, each program has its own pages in memory, and the VMM keeps tabs on who has what. It is a software solution to reroute what goes where, and how. As with most software virtualisation techniques, it is quite costly compared to doing the same thing in hardware. On VT, you need to drop to the VMM, figure out what memory point is being requested, where it is in actual memory, and pass that along to the memory controller. When the information comes back, you may have to fake the addresses again so the hosted app is oblivious to the fact that it is being virtualised. Instead of being done in hardware as are many other commands, VT manages memory in software.
Pacifica has an advantage in that the AMD64 architecture, as implemented on the K8 family of chips, all have a memory controller on the CPU. This allows Pacifica to pull some tricks, and those tricks are found in two new memory modes called Shadow Page Tables and Nested Page Tables. Both allow Pacifica to do in hardware much of what VT needs to do in software. µ
Part Two will be published tomorrow. The entire article in all of its parts is available on our subscriber site, details of which you can find here. The subscription service provides a page with no adverts and additional content, and costs $5 a month, or $50 a year.
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