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DDR3 DRAM gets ready for prime time

Fast as the fastest frame
Mon Feb 13 2006, 12:55
DURING THE recent ISSCC 2006 event, there was much focus on new stuff like IBM POWER6 componentry early insights, for instance. The 2.5 GHz 0.8 ns, 256 Mbit GDDR3 graphics memory chips from Hynix, as well as their 2 GHz 1 ns, 512 Mbit GDDR3 brethren from Infineon, were there too, whetting the appetites of 3-D graphics buffs expecting these rapid-fire memories in the next graphics card generation Nvidia 7900GTX and its ATI equivalent, I guess.

Talking about memory, one talk - not talked about much, though - was covering Elpida's "standard" DDR3 memory, the one meant for next-generation PCs and servers, for instance. Their 512 Megabit DDR3 SDRAM with a column access time of 8.75 ns (CL7 latency) and data transfer rate of 1.6 Gigabits per second (Gbps), or 1.6 GHz DDR3 for the laymen, would be the fastest DDR3 general purpose memory chip announced by now - all that at the usual 1.5v DDR3 voltage level, saving some electricity compared to the DDR2. What is more interesting is that, at an even lower 1.36 volts, the RAM runs fine at 1.333 GHz (DDR3-1333) grade with CL6 latency (8.4 ns total CAS time), which matches the CAS time of the fastest current DDR2 memory, the Corsair 5400UL (DDR2-667 CL3) at 1.9 volts.


All that in a 90 nm CMOS (not even the newer 80 nm process used by Samsung, for instance). How? Well, according to Elpida/Hitachi, their 8:4 data transfer multiplexer with shielded I/O lines, and dual-clock (separate for odd and even clock counts) latency counter to reduce cycle time to 1.2 ns (DDR3-1600 grade), combined with multiple on-dire termination merged output drivers. Why do you need all that stuff? Well, as DDR read two bits simultaneously from the DRAM memory array for each signal pin (i.e. for 100 MHz memory array, the outside transfer was 200 MHz per pin) and DDR2 read four bits for each signal pin, the DDR3 blanket-reads 8 bits, a whole byte, of date per each external signal pin, multiplexing 8 bits to one pin effectively using time division. So, a 200 MHz DDR3 memory array will correspond to 1,600 MHz effective outside per-pin thoughput.

Both Samsung and Infineon launched their DDR3 chips before Elpida, in fact early DDR3-1066 samples from these two vendors reached the OEMs late last year already. But these initial 512 Mbit 1.5 volt circuits aren't far ahead in performance compared to the best current DDR2 ones. However, the Elpida entry tempts with substantially higher performance, where ultrahigh bandwidth was not compromised by very high latency, yet the voltage was kept very low to ensure cool, power-saving operation even at DDR3-1333 CL6 - a very nice, clock-synchronised fit to the FSB1333 "Cointreaus"? Or maybe a dual-FSB1333 "Woodcrest" workstation variety where the improved latency and cheaper generic memory will be a preference over complicated, high-latency FB-DIMMs? Or, on the AMD side, the 1.36 volts level for the memory at DDR3-1333 is just a notch above the expected 1.3 volts Vcc for the upcoming 65 nm Athlon64 and Opteron series, making the on-chip memory controller integration that much easier, since the voltage levels are almost the same for the CPU cores, memory and the upcoming HyperTransport 3.0 links which will again double the data rate per port. After all, a dual-channel low-power, low-latency DDR3-1333 memory system would give you 21 GBytes/s of peak bandwidth, and probably close to, say, 18 GB/s Sandra memory benchmark if it was running via on-chip memory controller of a hypothetical 2007 Athlon64 CPU.

Knowing these are the first "chips on the block" of their kind, the performance is impressive. If you remember the initial DDR2 circuits, they were noticeably slower latency-wise compared to their DDR1 predecessors. In this case, the very first one (at least the Elpida entry) matches the best DDR2 parts in latency, and beats them twice in bandwidth, yet runs at or below 1.5 volts.

The DDR3 is still a year away from first mainstream PC implementations, although I do expect the initial support to appear late this year, in combination with volume production of these first chips from Elpida, Samsung and Infineon. The market researchers iSuppli expects DDR3 DRAM to finally replace DDR2 as the main volume product only in 2008, with a projected 55 percent market share that year. Of course, it's a long way till 2008, and there could be various potholes and roadblocks on the DDR3 highway before then. But again, the ultra-bloated Vista freight truck is coming along, in need of all the "performance and capacity fuel" it can get, so don't be surprised to see, among other things like quad-core CPUs and multi-super-duper GPUs, this DDR3 become a recommendation, then a requirement, in the upcoming Age of Vista - for Micro$oft-occupied lands only, that is: the Linux/UNIX 'free realms' can still do as they deem fit. µ


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