AMD talks about Barcelona

The chip, which will hit the shops in the middle of next year, will come with software that AMD claims deals with the performance issues related to Virtualisation software hypervisor.

According to Channel Insider, Ben Sander, a principal member of AMD's technical design staff, this should shove AMD right in the middle of Intel's Xeon chip market.

Sander said that by putting all four cores on a single slice of silicon, Barcelona has problems with its translation lookaside buffer, or TLB, which converts an operating system's relative memory addresses into the actual addresses used by the hardware. Hypervisors' use of shadow paging makes matters worse, making the chip complex to implement and can be fairly slow. AMD's big idea to get around this problem involves using "nested page tables" and the caching of memory addresses which speeds up the memory issue.

This takes pressure off the hypervisor, which normally would have to spend 75 percent of its time worrying about its memory.

Barcelona will have new instructions to shorten the chip's "world switch time" by about 25 percent and reduce the time it takes to switch between the guest operating system and hypervisor mode.

Each Barcelona processing core will have a 64KB level-one cache and 512KB level-two cache. All four cores share a 2MB level-three cache, but that can be made larger.

It will also handling a larger amount of physical memory than current Opterons, Sander said. µ

L'INQ
Channel Insider