Cambridge releases silicon IP 32-bit processor core

CAMBRIDGE CONSULTANTS said it has introduced a 32-bit RISC core which allows the deep embedding of applications.

The XAP3 core, the firm said, is optimised to use C compiler technology, so reducing memory needs and cutting down on power consumption.

The chip adds to Cambridge's 16-bit XAP2 processors, and continues to offer royalty free licensing. The XAP3 has a Von Neumann architecture which lets code and data be freely mixed together in its 4GB memory space. The core's RISC instruction set, assembly language and C compiler have been devised in parallel, said Cambridge, with the compile chain based on Codemist C.

Included is a programming/developing environment, xIDE, which includes compiler, linker, simulator and debugger. It is also readying an xIDE integrated development environment for the chip, which includes real time debugging and event monitoring.

A port for a Linux real time operating system is underway, while Cambridge also plans support for the Nuceus OS, the GCC compiler and TCP/IP.

Plus, it's pretty. µ

L'INQ
Cambridge Consultants