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Intel says 90 nano tech on 12-inch wafers ramping fast

Ireland starts first half of next year. Quality of silicon is strained
Tue Oct 28 2003, 09:27
CHIP GIANT INTEL said last year that it would introduce strained silicon technology into its 90 nanometer processors.

And the firm is ready to talk more about the project. It will introduce a paper at the International Electronics Meeting in Washington DC on December 9th - the title of that being A 90nm High Volume Manufacturing Logic Technology Featuring Novel 45nm Gate Length Strained Silicon CMOS Transistors.

Ninety nanometer logic will also include a 1.2 nanometer physical gate oxide thickness, the use of nickel silicide, seven layers of copper interconnect, carbon doped oxide low-k dielectric, 1µ2 6T SRAM cells, and all made on 300 millimeter (12-inch) silicon wafers.

Intel says that its 90 nano technology is currently being ramped to high volume for its Pentium and Centrino CPUs.

Three hundred millimeter fabs in Hillsboro Oregon, Albuquerque (Fab 11) are already producing 90 nano chips, while its Fab 24 in Leixlip, near Dublin Ireland, will start producing these wafers in the first half of 2004.

Intel says the 90 nano process has "experienced rapid yield improvement and the defect density is now down to the low level needed for high volume manufacturing".

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