NNTP shows chip firms how to build multi-cores

The core size of an Opteron, the author said, is 12 times the size of the instruction cache. A 486-like processor can be built in less area than that cache size, and the core could run at around 75% of the frequency of the Opteron.

The person said that if you assume that an Opteron is a 1.0 IPC machine, and the 486 is rated at 0.5 IPC, then once you take 12 of those 486-a-likes at a lower clock speed, you get 5 times the performance, on paper, of a single core Opteron if you measure in instructions per clock. Smaller, slower cores deliver more performance per area and per Watt, it is therefore suggested.

Subsequent discussion suggests that memory latency would be a big problem, with huge amounts of cache needed to keep all the separate cores occupied. The problem of how to handle memory control in dual-core chips is one that we are eagerly awaiting the differing solutions of AMD and Intel for. Commentators have suggested that the built-in memory controller of the Athlon 64 chip makes it easier to implement in a dual-core setup than the Pentium 4.

The original usenet posting is here, and there is some interesting discussion over on Aces Hardware. µ