Fujitsu eclipses Sun: The New SPARCle

OK, WE saw POWER5 at the Microprocessor Forum, but what about the SPARC front? After all, Solaris still has the greatest UNIX market share, and there are zillions of applications for the platform, over many years. While Sun may be in particularly deep troubles right now, the platform and its presence are still there, as well as determination by many of its users not to move to Wintel (or even Lintel) platforms.

Sun SPARC was rapidly falling behind the competitors in single-CPU performance for quite a number of years now - a combination of factors like underlying complicated SPARC architecture, Texas Instruments process performance, and Sun design team changes, led to a lackluster processor as a flagship CPU for Sun system line. In the UltraSPARC III, every single aspect of single-CPU performance, like sustainable execution rate in integer or FP, cache and memory performance, falls far behind the competitive products. No wonder Greg Papadopoulous was talking about avoiding per-CPU performance in favour of threaded "throughput computing" at Microprocessor Forum.

However, Fujitsu, one of the earliers SPARC group members, and producer of many early SPARC chips for Sun, evolved its own SPARC CPU line with a dedicated design team, and, with help of its in-house advanced process technology, soon eclipsed Sun's offerings. A year ago, they described SPARC64 V at this same forum, and soon after started shipping the machines with mainframe-like quality and high performance. These PRIMEPOWER machines, in 2 to 128-CPU setups, are among the fastest commercial SMP machines today.

Fujitsu SPARCmurai....
Fujitsu SPARC64 VI builds on the design of SPARC64 V, and integrates two enhanced SPARC64 V cores into a single chip. The enhancements are, as mentioned, a huge 6 MB, 12-way set associative on-chip L2 cache with very high bandwidth - 77 GB/s into each CPU, and 38 GB/s from each CPU at 2.4 GHz - hardware prefetch, and CPU core improvements like better branch prediction, FP MAC and register windowing, doubled translation buffer for memory paging, and more.

Add to it the base features of the SPARC64 V, like large 2 x 128 KB L1 caches and out-of-order 4-way superscalar execution, as well as full ECC across all the paths, and you got pretty much as far as SPARC can go. The shared L2 cache, which supports full bandwidth of both CPU cores simultaneously, also speeds up internal cache snoops between the two cores considerably. Finally, SPARC64 VI brings along the new "Jupiter" bus, with faster loads and stores due to its multiple unidirectional paths.

The chip is a real whopper, even in comparison to the current Madison Itanic2 from Intel: even though based on the 0.09 um copper process with 10 metal layers, SPARC 64 VI still takes an area of almost 400 mm2, occupied by some 690 million transistors. The chip, expected to start at 2.4 GHz, will operate at a 1.0 volt internal and 1.8 volt I/O voltages.

...and Sun SPARCowboy
US IV is to US III roughly what SPARC64 VI is to SPARC64 V, a dual-core follow-on with somewhat improved cache and memory architecture. SInce SPARC64 V was vastly superior to US III, would the same really apply when comparing SPARC64 VI to US IV ? Well, it seems so!

Basically, UltraSPARC IV is two UltraSPARC III 4-way superscalar in-order cores, each with 32+64 KB L1 cache, put together, with a physically shared, logically separate (?!?) external (therefore slower) L2 cache, and one major improvement - taken from US IIIi - an integrated DDR memory controller for a bit better local memory bandwidth and latency. The FirePlane system bus is, of course, inherited from US III.

The external L2 cache can go up to 16 MB per chip, 2 way set associative, partitioned as two 8 MB caches, one per CPU core. As you can see, there is a bit of improvement in overall bandwidth vs the US III, but nothing revolutionary. The chip, built in TI 0.13 um process, has some 66 million transistors on a roughly 350 mm2 die, not much smaller than the 690 million transistor SPARC64 VI die. It will initially run at the same clocks of 1.2 GHz as US III, with a 1.35 GHz version quickly following.

In summary, very little improvement, if any, in performance per thread - yes, you can double the CPU core density in US IV, but the fact that this SPARC design is at a standstill now for quite a few years shows its (lack of) future. The SPARC64 VI will easily be twice as fast as US IV on any job, single or multithreaded. So, Sun, why not just buy chips from Fujitsu? I'd love a nice cool workstation with two SPARC64 VI chips sitting on an ultrawide, ultrafast memory bus running, say, 32 GB RAM? µ