Greater fab diversity can lead to higher costs

Things such as sourcing, delays, production space, and other problems inherent in operating a third party fab-less semi and relying on foundries would be minimised by such an arrangement. It may in fact prove to be quite the opposite, and quite expensive to boot.

Apparently TSMC is quickly running out of 80nm space at their fabs, especially considering the whole slew of orders that Nvidia and ATI have placed recently for the fall lineup of products. To work around this issue both ATI and Nvidia have turned to UMC to provide more production space on their flavour of 80nm.

What could be wrong with seeking a second source for 80 nm parts? For starters the two 80 nm processes from TSMC and UMC are not compatible. A design ported to TSMC's 80nm process will most likely not work, or if it does, would work very slow on UMC's 80nm process. This is due to TSMC and UMC having non-compatible design libraries and standard cell layouts. So a chip designed for TSMC's 80 nm process would most likely not work on UMC's 80nm line.

A good example of the extra costs involved in such second sourcing appears to be ATI's RV560 and RV570. These two chips are functionally identical, except one is made by UMC on its lower performance 80nm process, while the other is based on TSMC's higher performing one. Though they are functionally identical, they are very much distinct designs from one another.

Let's go through the process here. ATI designs one of the chips - since I am not privy to such info, let's assume it is the RV570 - for TSMC's 80nm process. The Canadian firm uses TSMC's standard cell for that process, as well as the design libraries. ATI wrapped up verification of the design, taped it out, sent it off to have some masks made, and silicon starts rolling. Then ATI starts hearing of production space being limited, and decides to use UMC as the second source. It has to take UMC's standard cell and design libraries and apply it to the basic RV570 design.

Now, the chip makers don't have to start from scratch with the basic design, from what I understand, but the process is non-trivial. After the design has been ported to the UMC libraries and cells, then the entire design needs to go back through validation to make sure that it works as it should. The product is then taped out, masks made, and product starts rolling. Because one of the foundries did not have the production space needed for a design, more money and manpower had to be spent to get the second design up and running for the other foundry.

This is a very serious situation for these companies, as they do not relish the idea of spending more on a design to make sure that there is enough production to meet demand by utilising two foundries. If a company can balance out product SKUs and use a single source for that particular product, then it could eliminate some of this pressure. As we can see by ATI's example though, they are producing two essentially identical chips with different foundries, and the design costs of such a move are sure to hit the bottom line. Considering that a set of masks is around $1.5 million for a complex part, not to mention the time and money it takes to validate a chip, if these companies have to design a second chip for a second foundry, then belts are going to be tightening or the "savings" will be passed onto the consumer.

Let us explore another aspect of this fine mess. As processes move on, the physics behind depositing metal on silicon changes, and we are seeing this process slow down by a considerable degree. At 350nm, wafers typically took about eight weeks to process from start to finish. At 90nm, we are seeing a fairly consistent 14 weeks for the average wafer from start to finish. At 65nm this time is going to be spread out again to around 16 weeks. This is also the same for the hot-lots and super-hot-lots. Even if a company wants to fast track a wafer order, it is now taking upwards of 45 days vs. the 20 to 30 days that the older processes took.

The end result is that companies hoping to use multiple fabs for multiple designs better have their planning down pat well in advance, because the costs and potential delays of last minute changes could have dramatic repercussions on product release timelines. The price of competitiveness has again gone up in the fab-less semi world, and the risks that guys like Nvidia and ATI take to get a design to market ASAP are becoming much larger. µ