Intel's Otellini drops four processor bombshell, 24 hours from Tulsa

PAUL OTELLINI gave a refreshingly non-dull keynote to kick off IDF this fall, along with all the usual themes, convergence video, security and others, there were a few hidden gems. Most of these were found in the code names of Vanderpool, Lagrande, Tulsa and Tanglewood.

The big announcement is Vanderpool, or Vanderpool Technology (VT), which is Intel's way of putting VMWare functionality on a chip. The time for hardware partitioning is near, or at least the time for more announcements about hardware partitioning is near, they didn't put a time frame on this technology family.

In short, it allows you to run two virtual CPUs on a single CPU, basically like having a second PC in the box. This is not HT technology, which emulates a second CPU, the demo they showed had one 'computer' playing a Simpsons clip, and the other playing a game, rebooting, and then installing drivers. Nothing that you can't do now in software, the take home message is that this technology will decrease, or possibly eliminate the overhead of this increasingly important corporate mainstay.

The name is LaGrande, or secure hardware. The demo that they showed tells me that the the excessively bright people who designed this technology don't 'get' how security interacts with the real world. The main problem is that while LaGrande will prevent key sniffing and frame buffer scraping, what it will not do is, well, anything, once people compromise the keys. Think DeCSS for a nightmare scenario here, what happens if someone sends you malicious signed code. The phrase that bounces around in my head is Maginot right now.

The hardcore chip stuff was rather thin. Tanglewood has been announced previously, and Paul O said that it would be multi-core (yawn) and have 7x the performance as the current Itanium 2. Since it is multi- not dual- core, and it is not 8x as fast, I am lead to believe it will be 4 cored. The 7x speed, with 4x the core tells me that each core is less than twice as fast as the current chip. Maybe I am missing something, but unless die size doesn't increase much, this does not seem like the great leap forward I was expecting. If die size stays roughly the same, I am very wrong. Add another thing to my list of secrets to ferret out.

The last name dropped has a huge secret inadvertently placed in it. They announced Tulsa, the Xeon after Potomac, and said it would be dual core. Everyone oohed and aahed, wonders abound. This chip will be based on the Prescott core, or a successor, and will be a Xeon, meaning that all features will be 'turned on' long before they trickle down to the P4 line.

The bomb was that Otenelli said 'these will be dual cored, so they will show up as 4 processors'. That means that the enhanced HT in Prescott will not have more threads as rumored, but stick with two. Slips abound here at IDF. µ