There is reason in roasting egg
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Just how important is memory? We forget
At the moment, or rather, in the future, Hammer will debut with a single-channel DDR333 memory bus - though it's always possible AMD may increase this to a single-channel DDR400 bus. If it cares.
By the time the Athlon 64 launches, the P4 will be firmly established on an 800 MHz FSB of its own, with the equivalent of 6.4 Gb / s of memory bandwidth lined up against AMD's 2.7 Gb / s or possibly 3.2 Gb /s. By the numbers, that doesn't look so great. The numbers, however, as is often the case with raw statistics, don't tell the whole story.
The AthlonXP has, in fact, proved itself competitive to the Pentium 4 while having less than half the P4's bandwidth available to it for most of its life. While there are certain benchmarks that are heavily bandwidth dependent, performance in aggregate is not solely dependent on FSB / memory speed or CPU speed, but a combination of the two. The AthlonXP fell behind in the first half of 2002 due to AMD's inability to scale either the CPU's raw speed or its bus speed high enough to continue to compete with the P4. Assuming AMD can provide Barton's in sufficient quantity, the AthlonXP, by all appearances, has caught up to the P4 in terms of performance, yet still remains far behind in terms of GHz and available bandwidth.
It's possible, in fact, to predict how the P4s move to a higher FSB and how dual-channel DDR will affect its performance by comparing its best single-channel solution (the i845PE) to the new dual-channel solutions (E7205 and SiS 655) which provide 155% and 200% of the single-channel's bandwidth. Doubling the P4's bandwidth from 2.7 GB/s to 5.4 Gb/ s does, increase the overall performance of the system, but only by about 10% in most benchmarks. Clearly, dual-DDR by itself is not going to tilt the scales overwhelmingly towards the P4.
There are other benefits associated with an 800 MHz FSB / 800 MHz effective memory clock, including decreased latencies (assuming one is using DDR-I) and a higher front-side bus speed, both of which will provide speed increases of their own. P4 performance will benefit tremendously from these improvements, possibly jumping as much as 20-25% from its current position, assuming clock speed is held equal. It's an impressive feat of scaling for Santa Clara, but its not an insurmountable barrier for AMD.
The P4's dual DDR bus does provide the CPU with far more bandwidth than Athlon 64 will have, but as we've seen already, the P4 does not gain an overwhelming advantage over single-channel solutions from the move. The Athlon 64 will launch on an 800 MHz HT (rather than FSB) of its own, equaling the P4 in that regard, but with a memory controller running at least twice as fast as Chipzilla's best. The Athlon 64 will have to scale more aggressively in order to overcome the P4's bandwidth advantage, but, the K8 core is said to scale much better than the K7 did.
The numbers are going to change, but the overall situation won't. The P4 will continue to hold advantages in raw bandwidth and GHz speeds, while the Athlon 64 will be a far more efficient solution with a much faster memory controller. The P4 has been able to scale aggressively enough to surpass the AthlonXP, or at least keep it at bay, but whether or not it can do so against K8 remains to be seen. Intel's major speed boosts this year will be chipset-driven rather than CPU focused, so the Athlon 64 will likely go up against a 3.2 GHz or 3.4 GHz P4 at launch.
It's fair to say the P4 is going to be much more competitive against Hammer than was initially projected, but concluding that the P4's dual DDR solution will give it an edge AMD won't match is very premature. Until Opteron arrives and gives us some clue as to how Athlon 64 performance will look, the jury is still out. Unless this is some kind of kangaroo court and we'll all be jumped into a memory lynching. ยต
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