Here's more than you ever wanted to know about Silverthorne

A FEW DAYS AGO, Intel started talking about Silverthorne, its new ultra-low power CPU. It has some really unique properties, and the most relevant is that it is a ground up new design, not a shoehorning of reused parts.

The biggest thing about it is that Silverthorne is an in-order design, something not seen at Intel on an x86 part since the last century. This may not herald the return of steam trains, but Silverthorne is going to be an amazingly low power part. Since ISSCC, where it was talked about, is not a parts conference but a circuits conference, there were precious little details about the chip, eight bullet points in total. Let us fill in the gaps.

Sea-of-FUB-Licious Silverthorne die

The chip itself is what Intel is calling a Sea-of-FUBs design, with FUB standing for Functional Unit Blocks. This basically means it is pretty modular, and as you can see in the diagram above, the blocks are laid out in a pretty tidy fashion.

The official story is that it is a dual issue, in order pipeline with two threads per core. The switching algorithm is an on-demand SMT switch, not the much simpler round robin method some low power CPUs take. In the power envelope they are talking about, that is quite impressive.

Silverthorne is fully x86 ISA compatible, with all of the goodies including SSE3, VT and iAMD64, but Intel was a bit sketchy about features saying they might not all be productized on release. This is code for 'we will fuse some of the stuff off and charge you more when the new model come out without the fuse blown'. Whatever the case, that is damn impressive for such a low power part.

The physical chips is a little less than 25 square mm and packs 47M transistors, if you are careful, you can count them all in the pic above. The package it comes on is 13x14mm (the calculator is on under the accessories menu for those who need it), and is a micro flip chip BGA package with 441 balls. There is a pun here we won't touch, but let's just say it is small, but not as small at the Via 11x11mm package.

You can't talk power without talking clocks, and that is what Intel would not talk about. They would not say there are three SKUs, a 900MHz at the bottom, 1.86GHz at the top, and something in the middle. They have the option for 400/533FSBs, and the 900MHz version means they can do 1/4 clock dividers. Thsi means that the mid range part could be just about anywhere between the other two. Power is set at 600mW for the 900, 2W for the 1.86, and 1W for the middle one.

Knowing how power ramps, we guess the mid-SKU will be a 1333MHz/533FSB. Average power is said to be around 120Mw for the 900MHz version, but average is about the worst thing you can try to nail down in a meaningful sense. No matter, assume that power will be sipped, not slurped. One big gotcha here is that Intel is only guaranteeing the TDP if all thermal management features are fully enabled, so TDP may not always be TDP. This could have some potentially problematic throttling effects. We will see when things come ut.

How do they do this? One way is to put in a new low power state called C6, a different C6 from the one in the Via CN. Gotta love naming rights battles, but Via got there first. Intel would not say much about what C6 entails, yet, but they say that if C0 is 1.0x power, C6 is about .016x power. The big question is how long it takes to get in and out of C6, that more than the power use is the overriding issue.

Another power saving feature is that they have what is called split IO power, in layman's terms, they can turn off IO pins on the CPU. C6 keeps 21 pins alive. The FSB also has what is called CMOS mode, another power saving feature. The FSB works like any other FSB, but when it hits CMOS mode, it has a higher latency with much lower power use. You can pick which one you want depending on application.

The FSB connects to a rather unique chipset called Poulsbo, and it is pretty feature packed for a 22x22x2.3mm package. It is a single chip NB and SB, has integrated 2D and 3D as well as a video engine, USB 2.0, PCIe, SDIO2.0, and high def audio. It will push pixels from LVDS 1366 x 768 x 24b all the way up to 1080i while consuming 600-800mW average. Yuck, average. In any case, if you were wondering what happened to the PowerVR core, go by a Silverthorne box and see for yourself.

It supports 400 and 533FSBs as well as DDR2 at the same speeds, up to 1G worth. The graphics is all new, not the Gen 3.5 of it's predecessor Little River. They expect this much lower power version to score a bit less than LR in 3DMark, 500 in '03, 150 in '05. You will probably hit the 2.25W TDP doing this.

All this is tied together with a novel chip called Bangor, a power supply regulator. Intel showed this off at an IDF keynote last fall, but no one seemed to notice. It combines four power regulators in the same chip, cutting the space in half. It has CPU, chipset, memory and peripheral rails ranging from low to 5v. Bangor will occupy about 550mm^2, so figure a package of about a 24x24mm. It also supports something called Camarillo, but I can't find any references to that anywhere, so who knows?

Getting back to the core itself, it can issue two instructions per clock, one Int and one FP. Intel would not comment on pipeline stage count, but don't expect many, they eat power, and power is the enemy here. How does it do? Reliable sources are saying that it is about 10 per cent above Stealey. which sounds great until you realize that Stealey is an 800MHz Dothan and Silverthorne is at 1.86GHz. This is where in order bites you.

The future is already planned, the Silverthorne + Poulbo platform is called Menlow, and it will launch in Q2. The 2009 successor is called Moorestown, and it is basically a chipset shrink and supposedly whacks platform power by about 50 per cent while adding DDR3 and upping GPU performance by 50 per cent.

All in all, Intel seems to have done a damn good job with Silverthorne. Proof will be in the devices, but there doesn't seem to be many rough spots in the architecture. It is a high performance part for the power used, but won't be threatening Harpertown on TPC-C any time soon. It should enable a lot of very cool toys next quarter. µ