AMD waits for 65nm to crank up the megahurts

AMD's AM2 launch was considered a success by those in the OEM field, as it represented AMD's support for DDR-2 as well as reduced power consumption across the board.

Enthusiasts and others were not so impressed, however. Forums around the world resounded with calls to AMD to increase performance per clock, to provide a foil against the mighty Conroe, and to pull the rabbit out of the hat one more time. Unfortunately, AMD is hitting a pretty solid brick wall, and that wall is located at the Fab 30 and Fab 36 complex.

Oddly enough, AMD is a company that attempts to make money, which is a shocking idea to Socialists and Communists everywhere. Sometimes it even succeeds. Being able to succeed in the face of competition from Intel is actually quite impressive.

To be able to continue to make money against such a mighty foe, AMD has to focus on producing adequate quantities of processors without a large amount of waste. It can be a tricky balance, as AMD could pursue the almighty MHz with its process mix and achieve mind-numbing yields, or it could flood the market with chips at mediocre speeds with decent power consumption with incredibly high yields. These extremes are poor choices for AMD. But the bottom line for AMD and their success is simply process tech combined with a good design.

So why no improvements in IPC til 65nm? The answer to that question is transistor count and die size. AMD took its sweet time in getting AM2 out, and the engineers working on this product went through the design with a fine toothed comb.

Oh yes, they also included Pacifica (Virtualization), and a surprisingly robust DDR-2 controller with an improved Crossbar and Arbitrator. Power, Pacifica, and DDR-2 all combined made for a 20% increase in die size from the Rev. E cores to Rev. F. The dual core 512 KB L2 chips are 183 mm square, while the X2 1 MB L2 chips are a fantastical 230 mm square. Because of the way wafers are laid out, we are looking at around 25% to 30% less dies per wafer going from Rev. E parts to Rev. F. This is partially offset by Fab 36 ramping up its 90 nm process on 300 mm wafers, but it will cause a reduction in overall good dies per wafer coming from either Fab.

AMD is walking a tightrope. Not only do they have to push their dual core products in the face of Conroe, but they had to find different ways to market the product to consumers. Instead of throwing a lot more transistors at the problem and increasing IPC, all the while transitioning to DDR-2 as well as including Virtualization, AMD focused on power consumption and keeping the die sizes within “reasonable” parameters.

So what can we expect from the first 65 nm parts off the line? Probably something that few folks actually expect. Let me delve into one of the more overlooked properties of transistor design (well, at least to laymen like me). Basically the more stages in a pipeline means that the propagation delay in a signal is cut down and overall clockspeed can be increased, but more stages means that more transistors are being used. AMD is working with several partners to make sure that its 65 nm process is world class. This process encompasses embedded SiGe with dual stress liner and stress memorization technology on silicon on insulator- or e-SiGe with DSL and SMT on SOI for those so inclined. AMD and IBM have stated publicly that this technology allows for a 40% faster switching transistor than from a standard 65 nm design without all the three letter acronyms (TLA's). In a complex design like a CPU this could mean a theoretical 50% overall clockspeed increase going from AMD's 90 nm process to AMD/IBM's 65 nm process all the while staying within the same power envelope.

So, for AMD's first 65nm design, it had several choices. The first and most conservative choice would be to keep the Rev. F design essentially intact and port it to 65nm and explore the upper boundaries of clockspeed while taking a page from Intel's Pentium 4 book.

The second choice would be similar to what NVIDIA did with the 90nm G7x series and reduce the transistor count and die size, while improving the clockspeed by a smaller amount.

The final choice would be to transition those extra transistors in those redundant stages into more useful units, and increase IPC all the while keeping clockspeed in the same general area that current 90 nm processors enjoy, all the while shrinking the die size to more manageable levels. This final choice appears to be what AMD has in mind.

This bright fellow, here, as noted earlier, has made a careful inspection of die photos and has come to the conclusion that while Rev. G will be quite similar to the current Rev. F processors, AMD will include an extra complex decoder as well as an out of order load/store buffer and out of order read/write buffer.

This design decision is not exactly a conservative move from AMD, as many were expecting just a shrink of the existing Rev. F. core. Now, these extra units in Rev. G will improve IPC on the K8, but most likely will not allow the design to overtake Conroe and its ilk in overall performance. It will certainly allow AMD to get into spitting distance, and the extra transistor switching speeds that AMD's 65nm process promises will make for a much more compelling product than the current Rev. F/AM2 processors. Everything else looks the same though, which means the same 3 INT, 3 AGU, and most importantly the same 3 FPU/SSE units which can deliver 2 x 64 bit results per clock cycle peak. It will feature a higher IPC and be able to clock higher than the current Rev. F's, but Intel still looks to have a pretty hefty architectural advantage with its Core 2 products.

So, while AMD had its hands tied with the 90nm Rev. F processors, it looks to be stretching its wings with its first 65nm product that is due out in December.

It will take Intel a while to fully ramp the Conroe family of products, and until then AMD will still be selling 90 nm processors at a steady rate. Once 65 nm comes, then it will have a more compelling answer to Core 2. In late Spring of 2007 we will see the first dual core K8L processors introduced, and then we will have a whole nother ballgame. µ