The Tolapai emerges from under Intel's kimono

SLIDES FROM AN Intel presentation, have revealed the identity of a new entrant into the small form factor market from Intel.

The slides from the Powerpoint presentation were leaked to Chinese site HKEPC.

The Intel Tolapai architecture centres around a processor core based on the Pentium M architecture, and includes 256KB level 2 cache onboard.

The processor package has integrated MCH Northbridge and ICH Southbridge functionality - the 2nd slide demonstrates how a Pentium M, 915GM and ICH6 processor/chipset combination can be effectively replaced by one single Tolapai package.

Tolapai is listed at operating at 3 frequencies; 600MHz, 1.066GHz and 1.2GHz, with a TDP ranging from 13W to 22W.

The chip is based on an 1088-ball FCBGA package measuring at 3.75cm by 3.75cm via a 65nm process technology. The architecture has no 64-bit support.

Tolapai supports DDR2-800/667/533/400 in Dual Channel mode with ECC support up to 2GB. The architecture has full I/O functionality such as 3 x Gigabit Ethernet connections, PCI Express (1x8/2x4/2x1), 2 x USB 1.1/2.0, and 2 x SATA 1.0/2.0.

The Tolapai reference board design uses standard 12V ATX power, contains 2 DIMM slots for DDR-II 800, 3 x GbE ports, 1 PCI Express x8 slot (with 4 lanes), 2 SATA ports, 2 USB ports, plus further connectors for expansion bus interfaces.

Currently Tolapai is listed as supporting Red Hat Linux, FreeBSD and Windows Embedded XP, via its control application software.

This will be interesting reading to the designers and marketing folk behind AMD's Geode and Via's C7, both of which have targeted the SFF market space Intel is attempting to encroach.

Considering the decent performance of the Pentium M, found within the original Centrino-marketed laptops, this fully-featured integrated processor could give them both a run for their money. µ

See Also
PA Semi releases its chip
OQO upgrades world's smallest PC
Intel Thurley has early CSI interconnect
Intel plots successor to Santa Rosa with Penryn