Intel persists with dual-die to do or die

WHILE AMD IS trumpeting its 'Barcelona' 65nm native quad-core all over, Intel will have the semicon process advantage this year, with its 45 nm process and 'Penryn' CPUs.

Penryn's 410 million transistor per-die budget is nearly 50 per cent above that of Conroe with 4MB cache - therefore, besides increased 6MB L2 cache size, better FSB to use those dual-channel DDR3-1333 memories, and obvious clock speed and lower power benefits, there is space for few more things, like SSE4 additional media and supercomputing instructions, as well as Charlie's resurrected (and hopefully more useful this time!) HyperThreading.

There may be no chance of a native quad-core product until Nehalem. We hoped to see Intel do something about that, like say put four cores, each with say 2MB L2 cache, plus a shared 16MB L3 cache, on a single 1+ billion transistor die - or, at least, as we mentioned before, do a simple quad-core with a single 8MB shared L2 between them (however, multi-porting and ultrahigh bandwidth required may prove to be a challenge there).

For now, Intel has clearly indicated that the first Penryn-based quad-cores will be fashioned in the same dual-die module fashion as the current Kentsfield or Clovertown. Of course, the ever on-going FSB tune-ups and lower overall heat should still give us some very overclockable parts - how about working 4GHz/FSB 1600 quad core with air cooling this time? µ

See Also
2007 will be a good year for chips
Intel demonstrates that the Penryn is mightier than the Conroe