The tech is based on a low oxygen content copper alloy using a particular oxygen absorption process. The low power part is because NEC has designed by thinned dual damascene structure in molecular pore stacked low-k films.
It said that dielectric reliability is equivalent to the 65 nanometre node it developed by using a low damage etching process for the low-k material, and by using side wall protection of line trenches using ultra thin polymer films.
The copper interconnects are polycrystalline structures with many small grains, and the boundaries are particularly liable to failures. Metal oxide in the copper interconnects are responsible for failures, so NEC in collaboration with the Mirai project, uses a technique to soak up the oxygen atoms.
NEC claims that the technique means that there's a 50 per cent reduction in the chip size and a 20 per cent reduction in power consumption compared to the 65 nanometre nodes.
Forty five nanometres is pretty small. µ