Intel unveils new improvements, instructions in Prescott

HELLO LOUIS BURNS. Five minutes after you told the INQUIRER that you weren't going to tell us what the 13 instructions added to Prescott were, Intel held another presentation where they told everybody what they are.

Just in case you don't know yet, they are in five groups.

Joe Schutz, who manages the Prescott group at Intel quite charmingly told us everything.

The FP to integer conversion is FISTTP. The complex arithmetic instructions are ADDSUBPD, ADDSUBPS, MOVDDUP, MOVSHDUP, and MOVSLDUP.

The extra video encoding instruction is LDDQU. The SIMD FP using AOS (array of structures) instructions are HADDPD, HSUBPD, HADDPS, and HSUBPS.

And additional instructions for thread synchronisation are MONITOR and MWAIT.

Improved architecture for Prescott includes better pre-fetcher branch prediction, advanced power management, improvements to hyperthreading technology, the PNI above, La Grande support, better imul latency and additional WC buffers.

La Grande is the security feature Intel told us about at the last IDF, and includes protection in the CPU, at the platform level, and with software.

Prescott will scale to around 5GHz, while Intel reckons clock speeds will be 15-20GHz by 2010.

Intel will build it using 90 nanometer strained silicon technology, and seven layers of low-k metal interconnect, while it will have 1MB of cache and will start off with an 800MHz front side bus, suggesting that there are other plans afoot for this frequency.

So it's really a son of Pentium 4, rather than a Pentium 5.

We hope that makes everything clear, Louis.