RANDY ALLEN, Corporate veep of the server and workstation division at AMD was happy to pour cold water over yesterday’s announcements from Chipzilla.
In an interview with The Inq at HP's Tech@work conference in Barcelona Allen said: “On Nehalem, Intel is catching up with what we have. Barcelona is here. It is shipping with the largest number of OEMs we’ve ever had. We have level three cache, we've had integrated memory since 2003 and high speed serial links since 2006. I don‘t think there is anything new here.”
On Dunnington, Allen said that AMD’s forthcoming Shanghai will be 45nm. “In 2009 we will have enhancement to Hypertransport with HT3, DDR3 technology and eight cores or more. We’ll have four cores by the end of the year and you can expect to see eight cores in the 2009 timeframe,” he said.
On Larrabee, pointing at The Inq’s excellent coverage from yesterday which said “Intel is not as close to producing Larrabee products as we anticipated, however. It said that the multicore architecture will include a high performance wide SIMD vector processing unit which will support a set of vector instructions including floating point arithmetic, vector memory ops and conditional instructions.” Allen said: “Whatever that is, it is not x86. This is going to cause problems for software makers. It is a whole different software model which will present big issues.”
Allen said AMD was not immune to these issues but was better positioned to address them. µ
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