Intel is confident of a decent performance position in the current 1S, 2S market and across the 1S to 4S server space (some 95 per cent of the market, after all) once the Tigerton CPU with quad-FSB Caneland chipset comes out. The Core 2 family has pretty good integer and FP performance, the FSB still has a bit of speed potential (an official 1600MHz is not impossible, to my mind), and AMD isn't exactly experiencing perfect execution currently.
The CSI - common system interconnect (or call it coherent scalable interconnect, if you wish) - was originally associated with the Tukwilla Itanium generation. One that, in some now very old roadmaps, would have been out in the market right now. It would have been a nice example of good, year-1999 Alpha EV7 interface technology finally coming out on an Intel platform several years after the brutal Alphacide. But, oh well. EV7's simpler version, HyperTransport, has been doing exactly that already for the past three years anyway.
However, Tukwilla will, at best, appear sometime (late?) next year and, in the meantime, the same period, the "Nehalem" 2008 generation of Intel's X86 entries will also have CSI inside.
We can assume an even faster core (better integer, improved FP to compete against AMD Barcelona, a new implementation of hyper-threading), or to be precise four of them on a die. These will be combined with even larger caches, a multichannel DDR3 on-chip memory controller and, yes, the same very-fast 6.4Gbps-per-pin - at least on the high-end parts - CSI interconnect. Most probably four of them per chip in the now-familiar EV7 North-South-East-West configuration (by the way, the 1999 EV7 also had a fifth non-cache coherent channel just for I/O to keep I/O stuff from affecting the main SMP scalability - that's how advanced the murdered platform was).
This, of course, is way better than the current Opterons with only up to three HT channels sharing both SMP and I/O traffic, but about the same as Barcelona, where the highest-end parts are supposed to have four HT3 channels as well.
With AMD implementing sped-up HT3 in its upcoming 2007/2008 CPU, Intel can't afford to cripple the outside interconnect of its X86 CPUs just to keep Itanium's 'look' better. Therefore, Tukwilla and its supposed successor, Poulson, might only have their cores and caches to differentiate against the X86 in-house competition.
Now, if you look at the current SPECint and fp rates of Core 2 Quad 65nm processors, and even assume conservatively that they will only improve 30 per cent per core in initial Bloomfield Nehalems - although it will probably quite a bit more than that, especially for SPECfp, to address the AMD competition - and that the Tukwilla would get roughly the same 30 per cent per-core improvement vs 1.6GHz Montecito - we're not talking about a pretty picture for the good ship Itanic.
In fact, even the FP performance gulf will be gone. Even IBM's expensive POWER6 will have problems with Nehalems in this case - even if it really comes out at full 5GHz, and you ideally linearly scale the current 2.3GHz POWER5+ scores to that level. This doesn't usually happen, by the way.
In summary, while, in Nehalem, Intel focuses on delivering the ultimate 2008 winner X86 core with the last scalability problem - memory and interconnect - finally solved, there will be even fewer reasons to look at another, incompatible and expensive, 64-bit architecture - even one from the same house, in this case Itanium.
Yes, its huge register sets and so on will give benefits in certain apps like some HPC routines, but the comparative advantages vs their own X86 will be even less than before.
On the other hand, a good CSI implementation might at least save the Itanic's currently rusty ship hull from the icebergs like POWER6 and new Opterons in the life-saviing niches of the supercomputer and high-end server market, where its shared FSB was and still is affecting the scalability truly, badly, deeply.
Whether that will be enough to justify keeping the Itanic afloat beyond contractual obligations to HP and others - well that's up to Intel. Let us know what you think... µ
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